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TIMING REQUIREMENTS for Figure 1 : I
2
C Standard Mode (f
SCL
= 100kHz)
(1)
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
All specifications typical at – 40 ° C to +85 ° C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted.
2-WIRE STANDARD MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT
SNSVDD ≥ 1.6V 10 µ s
Reset low time
(2)
t
WL(RESET)
1.2V ≤ SNSVDD < 1.6V 13 µ s
SCL clock frequency f
SCL
100 kHz
Bus free time between a STOP and START
t
BUF
4.7 µ s
condition
Hold time (repeated) START condition t
HD, STA
4.0 µ s
Low period of SCL clock t
LOW
4.7 µ s
High period of the SCL clock t
HIGH
4.0 µ s
Setup time for a repeated START condition t
SU, STA
4.7 µ s
Data hold time t
HD, DAT
0 3.45 µ s
Data setup time t
SU, DAT
250 ns
Rise time of both SDA and SCL signals t
R
C
b
= total bus capacitance 1000 ns
Fall time of both SDA and SCL signals t
F
C
b
= total bus capacitance 300 ns
Setup time for STOP condition t
SU, STO
4.0 µ s
Capacitive load for each bus line C
b
C
b
= total capacitance of one bus line in pF 400 pF
Pulse width of spike suppressed t
SP
N/A N/A ns
(1) All input signals are specified with t
R
= t
F
= 5ns (30% to 70% of I/OVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) Refer to Figure 38 .
TIMING REQUIREMENTS for Figure 1 : I
2
C Fast Mode (f
SCL
= 400kHz)
(1)
All specifications typical at – 40 ° C to +85 ° C, SNSVDD = I/OVDD = +1.2V to +3.6V, unless otherwise noted.
2-WIRE FAST MODE PARAMETERS TEST CONDITIONS MIN MAX UNIT
SNSVDD ≥ 1.6V 10 µ s
Reset low time
(2)
t
WL(RESET)
1.2V ≤ SNSVDD < 1.6V 13 µ s
SCL clock frequency f
SCL
400 kHz
Bus free time between a STOP and START
t
BUF
1.3 µ s
condition
Hold time (repeated) START condition t
HD, STA
0.6 µ s
Low period of SCL clock t
LOW
1.3 µ s
High period of the SCL clock t
HIGH
0.6 µ s
Setup time for a repeated START condition t
SU, STA
0.6 µ s
Data hold time t
HD, DAT
0 0.9 µ s
Data setup time t
SU, DAT
100 ns
Rise time of both SDA and SCL signals t
R
C
b
= total bus capacitance 20 + 0.1 × C
b
300 ns
Fall time of both SDA and SCL signals t
F
C
b
= total bus capacitance 20 + 0.1 × C
b
300 ns
Setup time for STOP condition t
SU, STO
0.6 µ s
Capacitive load for each bus line C
b
C
b
= total capacitance of one bus line in pF 400 pF
Pulse width of spike suppressed t
SP
0 50 ns
(1) All input signals are specified with t
R
= t
F
= 5ns (30% to 70% of I/OVDD) and timed from a voltage level of (V
IL
+ V
IH
)/2.
(2) Refer to Figure 38 .
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