Datasheet
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DATA REGISTERS
X, Y, Z1, Z2, AUX, TEMP1 and TEMP2 REGISTERS
Register Map
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
PDST— Power down status. This bit reflects the setting of the PND0 bit in Control Byte 0. When this bit shows '0',
it indicates A/D converter bias circuitry is still powered on after each conversion and before the next sampling;
otherwise, it indicates A/D converter bias circuitry is powered down after each conversion and before the next
sampling. However, it is powered down between conversion sets. Because this status bit is synchronized with
the internal clock, it does not reflect the setting of the PND0 bit until a pen touch is detected or a converter
function is running.
ID[1:0] Device ID bits: These bits represent the version ID of TSC2004. This version defaults to '00'.
The data registers of the TSC2004 hold data results from conversions. All of these registers default to 0000h
upon reset.
The results of all A/D conversions are placed in the appropriate data registers, as described in Table 10 . The
data format of the result word (R) of these registers is right-justified, as shown in Table 29 .
Table 29. Internal Register Format
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
The TSC2004 has several 16-bit registers that allow control of the device, as well as providing a location to store
results from the TSC2004 until read out by the host microprocessor. Table 30 shows the memory map.
Table 30. Register Content and Reset Values
(1)
RESET
A3-A0 REGISTER VALUE
(HEX) NAME D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (HEX)
0 X 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
1 Y 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
2 Z1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
3 Z2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
4 AUX 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
5 Temp1 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
6 Temp2 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
Rsvd
7 Status S15 S14 S13 S12 S11 S10 S9 0 S7 S6 S5 S3 S2 S1 S0 0004
(2)
8 AUX High 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0FFF
9 AUX Low 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
A Temp High 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0FFF
B Temp Low 0 0 0 0 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
C CFR0 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 4000
D CFR1 0 0 0 0 R11 R10 R9 R8 0 0 0 0 0 R2 R1 R0 0000
E CFR2 R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 0 R4 R3 R2 R1 R0 0000
Converter
Rsvd
F Function R15 R14 R13 R12 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 0000
(2)
Select Status
(1) For all combination bits, the pattern marked as Rsvd (reserved) must not be used. The default pattern is read back after reset.
(2) This bit is reserved.
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