Datasheet
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Configuration Register 1
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
Table 18. Sense Time Selection
SNS2 SNS1 SNS0 SENSE TIME (t
SNS
)
0 0 0 32 µ s
0 0 1 96 µ s
0 1 0 544 µ s
0 1 1 608 µ s
1 0 0 2.080ms
1 0 1 2.144ms
1 1 0 2.592ms
1 1 1 2.656ms
DTW— Detection of pen touch in wait (patent pending). Writing a '1' to this bit enables the pen touch detection in
the background while waiting for the host to issue the converter function in host-initiated/controlled modes. This
background detection allows the TSC2004 to pull high at PINTDAV to indicate no pen touch detected while
waiting for the host to issue the converter function. If the host polls a high state at PINTDAV before the convert
function is sent, the host can abort the issuance of the convert function and stay in the polling PINTDAV mode
until the next pen touch is detected.
LSM— Longer sampling mode. When this bit is set to '1', the extra 500ns of sampling time is added to the normal
sampling cycles of each conversion. This additional time is represented as approximately two internal oscillator
clock cycles. For SNSVDD = 1.2V at – 40 ° C, the LSM bit should be set to '1' so that the sampled signal has
enough time to settle.
Configuration register 1 (CFR1) defines the connection test-bit modes configuration and batch delay selection.
Table 19. Configuration Register 1 (Reset Value = 0000h)
MSB LSB
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Resrvd Resrvd Resrvd Resrvd TBM3 TBM2 TBM1 TBM0 Resrvd Resrvd Resrvd Resrvd Resrvd BTD2 BTD1 BTD0
TBM3-TBM0— Connection test-bit modes (patent pending). These bits specify the mode of test bits used for the
predefined range of the combined X-axis and Y-axis touch screen panel resistance (R
TS
).
Table 20. Touch Screen Resistance Range and Test-Bit Modes
TEST-BIT MODES
R
TS
TBM3 TBM2 TBM1 TBM0 (k Ω )
0 0 0 0 0.17
0 0 0 1 0.17 < R
TS
≤ 0.52
0 0 1 0 0.52 < R
TS
≤ 0.86
0 0 1 1 0.86 < R
TS
≤ 1.6
0 1 0 0 1.6 < R
TS
≤ 2.2
0 1 0 1 2.2 < R
TS
≤ 3.6
0 1 1 0 3.6 < R
TS
≤ 5.0
0 1 1 1 5.0 < R
TS
≤ 7.8
1 0 0 0 7.8 < R
TS
≤ 10.5
1 0 0 1 10.5 < R
TS
≤ 16.0
1 0 1 0 16.0 < R
TS
≤ 21.6
1 0 1 1 21.6 < R
TS
≤ 32.6
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Only for short-circuit panel test
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