Datasheet

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REGISTER ACCESS
ReadCycle:Sequential,fromRegisterAddressmh to(m+n)h
(2) (3)
I C
2
Read-AddressingByte
Register(Address=mh)Content
START
I C
2
SlaveAddressS 1 AA
DataByte1/2
(HIGHByte)
DataByte2/2
(LOWByte)
A
1
8 8
7
Register(Address=(m+1)h)Content
Register(Address=(m+n)h)Content
A
DataByte1/2
(HIGHByte)
DataByte2/2
(LOWByte)
A
8 8
A
DataByte1/2
(HIGHByte)
DataByte2/2
(LOWByte)
N P
8 8 NACK
STOP
(1)
FromMastertoSlave
A=Acknowledge(SDALOW)
N=NotAcknowledge(SDAHIGH)
S=STARTCondition
P=STOPCondition
Sr=RepeatedSTARTCondition
FromSlavetoMaster
NOTES:
(1)Inordertostartthenextsequence,aSTOPconditionmustbefollowedbyaSTARTcondition.IfnoSTOPis
used,thenaRepeatedSTARTmustbeused.AlsonotethatisaSTOPconditionisissuedinHigh-Speed
mode,themodewillreverttothepreviousmode:FastorStandard.
(2)mhisahexadecimalnumber.
(3)If(m+n)hisgreaterthanFh,then(m+n)hismodulo16.
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
Data access begins with the master issuing a START (or repeated START) condition followed by the 7-bit
address and a read bit (R/ W = 1; see Table 5 ). When the eighth bit has been received and the address matches,
the slave issues an acknowledge by pulling SDA low for one clock cycle (ACK = 0). The first byte of serial data
then follows. After the first byte has been sent by the slave, it releases the SDA line for the master to issue an
acknowledge (ACK = 0). The slave issues the second byte of serial data upon receiving the acknowledgement
from the master (D7-D0), followed by a not-acknowledge bit (ACK = 1) from the master to indicate that the last
data byte has been received. The master then issues a STOP condition (P) or repeated START (Sr), which ends
the read cycle, as shown in Figure 36 and Figure 37 . If the master issues a not-acknowledge (ACK = 1) after
receipt of the first data byte, the master must then issue a stop condition (P) to reset the registers. If the master
is not ready to receive the second data byte, it should issue the acknowledge (ACK = 0), or the master should
stretch the clock. Upon restart of the clock, the second byte of data can be received by the master.
Figure 36. Sequential Read Cycle
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