Datasheet

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START A WRITE CYCLE
WriteCycle
I CSlaveAddress
2
I C
2
Write-
AddressingByte
ACK STOP
(1)
START
1 C3 C2 C1 C0
RM
SWRST
STS
ControlByte1A AS P0
17 8
I C
2
SlaveAddress
I CWrite-
AddressingByte
2
ACK
STOP
(1)
STOP
(1)
0 0A3 A2 A1 A0
Rsvd
PND0
ControlByte0
DataByte1/2
(HIGHByte)
DataByte2/2
(LOWByte)
A
A A
A PS 0
17
I C
2
SlaveAddress
I CWrite-
AddressingByte
2
MixedM(ControlByte1orControlByte0withReadBit)
PlusN(ControlByte0withDataBytes),SeparatedbyTSC ACKs
(M+Nx3)x8
AA
A A PS 0
17
8 8 8
ConverterFunction Select
TSCInternalRegisterAddressforWriteData
I C
2
SlaveAddress
I CWrite-
AddressingByte
2
ACK
STOP
(1)
0 1A3 A2 A1 A0
Rsvd
PND0
ControlByte0A
A P
S 0
17 8
TSCInternalRegisterStartingAddressmh
(2)
START
START
START
FromMastertoSlave
A=Acknowledge(SDALOW)
N=NotAcknowledge(SDAHIGH)
S=STARTCondition
P=STOPCondition
Sr=RepeatedSTARTCondition
FromSlavetoMaster
NOTES:
(1)Inordertostartthenextsequence,aSTOPconditionmustbefollowedbyaSTARTcondition.IfnoSTOPis
used,thenaRepeatedSTARTmustbeused.AlsonotethatisaSTOPconditionisissuedinHigh-Speed
mode,themodewillreverttothepreviousmode:FastorStandard.
(2)mhisahexadecimalnumber.
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
A write cycle begins when the master issues the slave address to the TSC2004. The slave address consists of
seven address bits and a write bit (R/ W = 0; see Table 5 ). When the eighth bit has been received and the
address matches the AD1-AD0 address input pin setting, the TSC2004 issues an acknowledge bit by pulling
SDA low for one additional clock cycle (ACK = 0); see Figure 34 .
When the master receives the acknowledge bit from the TSC2004, the master writes the input control byte to the
slave; see Table 5 . After the control byte is received by the slave, the slave issues another acknowledge bit by
pulling SDA low for one clock cycle (ACK = 0). The master then ends the write cycle by issuing a STOP or
repeated START condition; see Figure 35 .
Figure 35. Write Cycle
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