Datasheet

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DIGITAL INTERFACE
ADDRESS BYTE
I CWrite-AddressingByte
2
AD11 0 0 1 0 AD0 0 A
I CRead-AddressingByte
2
AD1S/Sr 1 0 0 1 0 AD0 1 A
STARTor
RepeatedSTART
ACK
S/Sr
STARTor
RepeatedSTART
ACK
FromMastertoSlave
A=Acknowledge(SDALOW)
S=STARTCondition
Sr=RepeatedSTARTCondition
FromSlavetoMaster
CONTROL BYTE
TSC2004
SBAS408E – JUNE 2007 – REVISED MARCH 2008
The TSC2004 has a 7-bit slave address word. The first five bits (MSBs) of the slave address are factory-preset to
comply with the I
2
C standard for A/D converters and are always set at '10010'. The logic state of the address
input pins (AD1-AD0) determine the two LSBs of the device address to activate communication. Therefore, a
maximum of four devices with the same preset code can be connected on the same bus at one time.
The AD1-AD0 address inputs are only read during a power-up of the device, and should be connected to a digital
supply (I/OVDD), or digital ground (DGND). The slave address is latched into the TSC2004 on the falling edge of
SCL after the read/write bit has been received by the slave.
The last bit of the address byte (R/ W) defines the operation to be performed. When set to a '1', a read operation
is selected; when set to a ‘ 0 ’ , a write operation is selected. Following the START condition, the TSC2004
monitors the SDA bus, checking the device type identifier being transmitted. Upon receiving the '10010' code, the
appropriate device select bits, and the R/ W bit, the slave device outputs an acknowledge signal on the SDA line.
Table 4. I
2
C Slave Address Byte
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 1 0 AD1 AD0 R/ W
Bit D0: R/ W
1: I
2
C master read from TSC (I
2
C read addressing).
0: I
2
C master write to TSC (I
2
C write addressing).
Figure 34. I
2
C Bus Addressing (Slave Address Byte Format)
Table 5. Control Byte Format:
Start a Conversion and Mode Setting
MSB LSB
D7 D6 D5 D4 D3 D2 D1 D0
1
C3 C2 C1 C0 RM SWRST STS
(Control Byte 1)
0 Reserved
A3 A2 A1 A0 PND0 R/ W
(Control Byte 0) (Write '0')
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