Datasheet

12
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TSC2000
SBAS257
MSB LSB
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
R/W PG3 PG2 PG1 PG0 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 X X X X X
TABLE I. TSC2000 Command Word.
PG3 PG2 PG1 PG0 PAGE ADDRESSED
0000 0
0001 1
0 0 1 0 Reserved
0 0 1 1 Reserved
0 1 0 0 Reserved
0 1 0 1 Reserved
0 1 1 0 Reserved
0 1 1 1 Reserved
1 0 0 0 Reserved
1 0 0 1 Reserved
1 0 1 0 Reserved
1 0 1 1 Reserved
1 1 0 0 Reserved
1 1 0 1 Reserved
1 1 1 0 Reserved
1 1 1 1 Reserved
TABLE II. Page Addressing.
pulled to ground through the touch screen and
PENIRQ
output goes LOW due to the current path through the panel
to GND, initiating an interrupt to the processor. During the
measurement cycles for the X- and Y-positions, the X+ input
will be disconnected from the
PENIRQ pull-down transistor to
eliminate any leakage current from the pull-up resistor to flow
through the touch screen, thus causing no errors.
In modes where the TSC2000 needs to detect if the screen
is still touched (for example, when doing a
PENIRQ -initiated
X, Y, and Z conversion), the TSC2000 must reset the drivers
so that the 50kΩ resistor is connected again. Due to the high
value of this pull-up resistor, any capacitance on the touch
screen inputs will cause a long delay time, and may prevent
the detection from occurring correctly. To prevent this, the
TSC2000 has a circuit which allows any screen capacitance
to be “precharged”, so that the pull-up resistor doesn’t have
to be the only source for the charging current. The time
allowed for this precharge, as well as the time needed to
sense if the screen is still touched, can be set in the
Configuration Control register.
This illustrates the need to use the minimum capacitor values
possible on the touch screen inputs. These capacitors may
be needed to reduce noise, but too large a value will increase
the needed precharge and sense times, as well as panel
voltage stabilization time.
DIGITAL INTERFACE
The TSC2000 communicates through a standard SPI bus.
The SPI allows full-duplex, synchronous, serial communica-
tion between a host processor (the master) and peripheral
devices (slaves). The SPI master generates the synchroniz-
ing clock and initiates transmissions. The SPI slave devices
depend on a master to start and synchronize transmissions.
A transmission begins when initiated by a master SPI. The
byte from the master SPI begins shifting in on the slave
MOSI pin under the control of the master serial clock. As the
byte shifts in on the MOSI pin, a byte shifts out on the MISO
pin to the master shift register.
The idle state of the serial clock for the TSC2000 is LOW,
which corresponds to a clock polarity setting of 0 (typical
microprocessor SPI control bit CPOL = 0). The TSC2000
interface is designed so that with a clock phase bit setting of
1 (typical microprocessor SPI control bit CPHA = 1), the
master begins driving its MOSI pin and the slave begins
driving its MISO pin on the first serial clock edge. The
SS pin
should idle HIGH between transmissions. The TSC2000 will
only interpret command words which are transmitted after the
falling edge of
SS .
TSC2000 COMMUNICATION PROTOCOL
The TSC2000 is entirely controlled by registers. Reading and
writing these registers is accomplished by the use of a 16-bit
command, which is sent prior to the data for that register. The
command is constructed as shown in Table I.
The command word begins with a R/W
bit, which specifies
the direction of data flow on the serial bus. The following four
bits specify the page of memory this command is directed to,
as shown in Table II. The next six bits specify the register
address on that page of memory to which the data is
directed. The last five bits are reserved for future use.