Datasheet

1−2
One of the key elements for reducing the TSB82AA2B operational power requirements is the TI advanced CMOS
process and the implementation of an internal 1.8-V core, which is supplied by an improved integrated 3.3-V to 1.8-V
voltage regulator. The TSB82AA2B implements a next-generation voltage regulator that is more efficient than its
predecessors, thus providing an overall reduction in the device operational power requirements especially when
operating in D3
cold
using auxiliary power. In fact, the TSB82AA2B device fully supports D0, D1, D2, and D3
hot/cold
power states as specified in the PC 2001 Design Guide requirements and the PCI Power-Management Specification.
PME wake event support is subject to operating system support and implementation.
As required by the 1394 Open Host Controller Interface Specification (OHCI) and IEEE Std 1394a-2000, internal
control registers are memory mapped and nonprefetchable. The PCI configuration header is accessed through
configuration cycles as specified by the PCI Local Bus Specification, and provides plug-and-play (PnP) compatibility.
Furthermore, the TSB82AA2B device is fully compliant with the latest PCI Local Bus Specification, PCI Bus Power-
Management Interface Specification, IEEE Draft Std 1394b, IEEE Std 1394a-2000, and 1394 Open Host Controller
Interface Specification (see Section 1.3, Related Documents, for a complete list).
1.2 Features
The TSB82AA2B device supports the following features:
• Single 3.3-V Supply (1.8-V Internal Core Voltage With Regulator)
• Available in Industrial (−40°C to 85°C) and Commercial (0°C to 70°C) Temperature Ranges
• 3.3-V and 5-V PCI Signaling Environments
• Serial Bus Data Rates of 100M bit/s, 200M bit/s, 400M bit/s, and 800M bit/s
• Physical Write Posting of up to Three Outstanding Transactions
• Serial ROM or Boot ROM Interface Supports 2-Wire Serial EEPROM Devices
• 33-MHz/64-Bit and 33-MHz/32-Bit Selectable PCI Interface
• Multifunction Terminal (MFUNC Terminal 1)
− PCI_CLKRUN
Protocol Per PCI Mobile Design Guide
− General-Purpose I/O (GPIO)
− CYCLEIN/CYCLEOUT for External Cycle Timer Control for Customized Synchronization
• PCI Burst Transfers and Deep FIFOs to Tolerate Large Host Latency
− Transmit FIFO — 5K Asynchronous
− Transmit FIFO — 2K Isochronous
− Receive FIFO — 2K Asynchronous
− Receive FIFO — 2K Isochronous
• D0, D1, D2, and D3 Power States and PME
Events Per PCI Bus Power-Management Interface
Specification
• Programmable Asynchronous Transmit Threshold
• Isochronous Receive Dual-Buffer Mode
• Out-of-Order Pipelining for Asynchronous Transmit Requests
• Register Access Fail Interrupt When PHY SYSCLK Is Not Active
• Initial Bandwidth Available and Initial Channels Available Registers
• Digital Video and Audio Performance Enhancements
• Fabricated in Advanced Low-Power CMOS Process
• Packaged in 144-Terminal LQFP (PGE)