Datasheet

5−5

Table 5−3. Link Enhancement Register Description (Continued)

BIT FIELD NAME TYPE DESCRIPTION

6 RSVD R This bit is not assigned in the TSB82AA2B follow-on products, since this bit location loaded by the

serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host

controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control

5−3 RSVD R Reserved. Bits 5−3 return 0s when read.

2 enab_insert_idle RSC Enable insert idle (OHCI-Lynx compatible). When the PHY layer has control of the

PHY_CTL0−PHY_CTL1 internal control lines and PHY_DATA0−PHY_DATA7 internal data lines and

the link requests control, the PHY drives 11b on the PHY_CTL0−PHY_CTL1 internal lines. The link

can then start driving these lines immediately. Setting bit 2 to 1 inserts an idle state, so the link waits

one clock cycle before it starts driving the lines (turnaround time).

1 enab_accel RSC Enable acceleration enhancements (OHCI-Lynx compatible). When bit 1 is set to 1, the PHY is

notified that the link supports IEEE Std 1394a-2000 acceleration enhancements, that is,

ack-accelerated, fly-by concatenation, etc. It is recommended that this bit be set to 1.

0 RSVD R Reserved. Bit 0 returns 0 when read.