Datasheet

5−4
5.5 Link Enhancement Control Register
This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCI
offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM,
if one is present, as noted in the bit descriptions below. If the bits are to be initialized by software, then the bits must
be initialized prior to setting bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see
Section 4.16, Host Controller Control Register). See Table 5−3 for a complete description of the register contents.
Offset: A88h set register
A8Ch clear register
Type: Read/Set/Clear, Read/Write, Read only
Default: 0000 0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0
Table 5−3. Link Enhancement Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−16 RSVD R Reserved. Bits 31−16 return 0s when read.
15 dis_at_pipeline RSC Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled.
14 RSVD R Reserved
13−12 atx_thresh RSC This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the
TSB82AA2B device retries the packet, it uses a 2-Kbyte threshold, resulting in a store-and-forward
operation.
00 = Threshold ~4K bytes resulting in a store-and-forward operation (default)
01 = Threshold ~1.7K bytes
10 = Threshold ~1K bytes
11 = Threshold ~512 bytes
These bits fine tune the asynchronous transmit threshold. For most applications, the 1.7-K threshold
is optimal. Changing this value may increase or decrease the 1394 latency depending on the average
PCI bus latency.
Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these thresholds
or when an entire packet has been checked into the FIFO. If the packet to be transmitted is larger
than the AT threshold, the remaining data must be received before the AT FIFO is emptied; otherwise,
an underrun condition occurs, resulting in a packet error at the receiving node. As a result, the link
then commences store-and-forward operation — that is, wait until it has the complete packet in the
FIFO before retransmitting it on the second attempt, to ensure delivery.
An AT threshold of 4K results in store-and-forward operation, which means that asynchronous data
is not transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 4K
results in only complete packets being transmitted.
Note that this device always uses store-and-forward when the asynchronous transmit retries register
at OHCI offset 08h (see Section 4.3, Asynchronous Transmit Retries Register) is cleared.
11 RSVD R Reserved. Bit 11 returns 0 when read.
10 RSVD R Reserved. Bit 10 returns 0 when read.
9 enab_aud_ts R/W Enable audio/music CIP timestamp enhancement. When bit 9 is set to 1, the enhancement is enabled
for audio/music CIP transmit streams (FMT = 10h).
8 enab_dv_ts RSC Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV
CIP transmit streams (FMT = 00h).
7 enab_unfair RSC Enable asynchronous priority requests (OHCI-Lynx compatible). Setting bit 7 to 1 enables the link
to respond to requests with priority arbitration. It is recommended that this bit be set to 1.