Datasheet

4−39
4.45 Isochronous Receive Context Command Pointer Register
The isochronous receive context command pointer register contains a pointer to the address of the first descriptor
block that the TSB82AA2B device accesses when software enables an isochronous receive context by setting bit 15
(run) in the isochronous receive context control register (see Section 4.44, Isochronous Receive Context Control
Register) to 1. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).
Type: Read only
Offset: 40Ch + (32 * n)
Default: XXXX XXXXh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default X X X X X X X X X X X X X X X X
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default X X X X X X X X X X X X X X X X