Datasheet

4−35
4.41 Asynchronous Context Command Pointer Register
The asynchronous context command pointer register contains a pointer to the address of the first descriptor block
that the TSB82AA2B device accesses when software enables the context by setting bit 15 (run) of the asynchronous
context control register (see Section 4.40, Asynchronous Context Control Register) to 1. See Table 4−33 for a
complete description of the register contents.
Type: Read/Write/Update
Offset: 18Ch (ATRQ)
1ACh (ATRS)
1CCh (ArRQ)
1ECh (ArRS)
Default: XXXX XXXXh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default X X X X X X X X X X X X X X X X
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default X X X X X X X X X X X X X X X X
Table 4−33. Asynchronous Context Command Pointer Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−4 descriptorAddress RWU Contains the upper 28 bits of the address of a 16-byte aligned descriptor block
3−0 Z RWU Indicates the number of contiguous descriptors at the address pointed to by the descriptor address.
If Z is 0, it indicates that the descriptorAddress field (bits 31−4) is not valid.