Datasheet

4−27
4.33 PHY Control Register
The PHY control register reads from or writes to a PHY register. See Table 4−26 for a complete description of the
register contents.
Type: Read/Write/Update, Read/Write, Read/Update, Read only
Offset: ECh
Default: 0000 0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−26. PHY Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 rdDone RU Bit 31 is cleared to 0 by the TSB82AA2B device when either bit 15 (rdReg) or bit 14 (wrReg) is set to
1. This bit is set to 1 when a register transfer is received from the PHY device.
30−28 RSVD R Reserved. Bits 30−28 return 0s when read.
27−24 rdAddr RU This field is the address of the register most recently received from the PHY device.
23−16 rdData RU This field is the contents of a PHY register that has been read.
15 rdReg RWU Bit 15 is set to 1 by software to initiate a read request to a PHY register, and is cleared by hardware
when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1
simultaneously.
14 wrReg RWU Bit 14 is set to 1 by software to initiate a write request to a PHY register, and is cleared by hardware
when the request has been sent. Bits 14 (wrReg) and 15 (rdReg) must not both be set to 1
simultaneously.
13−12 RSVD R Reserved. Bits 13−12 return 0s when read.
11−8 regAddr R/W This field is the address of the PHY register to be written or read.
7−0 wrData R/W This field is the data to be written to a PHY register and is ignored for reads.
4.34 Isochronous Cycle Timer Register
The isochronous cycle timer register indicates the current cycle number and offset. When the TSB82AA2B device
is cycle master, this register is transmitted with the cycle start message. When the TSB82AA2B device is not cycle
master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message
is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference.
See Table 4−27 for a complete description of the register contents.
Type: Read/Write/Update
Offset: F0h
Default: XXXX XXXXh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default X X X X X X X X X X X X X X X X
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default X X X X X X X X X X X X X X X X
Table 4−27. Isochronous Cycle Timer Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−25 cycleSeconds RWU This field counts seconds [rollovers from bits 24−12 (cycleCount field)] modulo 128.
24−12 cycleCount RWU This field counts cycles [rollovers from bits 11−0 (cycleOffset field)] modulo 8000.
11−0 cycleOffset RWU This field counts 24.576-MHz clocks modulo 3072, that is, 125 μs. If an external 8-kHz clock
configuration is being used, this field must be cleared to 0s at each tick of the external clock.