Datasheet

viii
Table Title Page
4−6 Configuration ROM Header Register Description 4−6. . . . . . . . . . . . . . . . . . . .
4−7 Bus Options Register Description 4−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−8 Configuration ROM Mapping Register Description 4−10. . . . . . . . . . . . . . . . . . .
4−9 Posted Write Address Low Register Description 4−10. . . . . . . . . . . . . . . . . . . .
4−10 Posted Write Address High Register Description 4−10. . . . . . . . . . . . . . . . . . . .
4−11 Vendor ID Register Description 4−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−12 Host Controller Control Register Description 4−12. . . . . . . . . . . . . . . . . . . . . . . .
4−13 Self-ID Count Register Description 4−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−14 Isochronous Receive Channel Mask High Register Description 4−15. . . . . . .
4−15 Isochronous Receive Channel Mask Low Register Description 4−16. . . . . . . .
4−16 Interrupt Event Register Description 4−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−17 Interrupt Mask Register Description 4−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−18 Isochronous Transmit Interrupt Event Register Description 4−21. . . . . . . . . . .
4−19 Isochronous Receive Interrupt Event Register Description 4−22. . . . . . . . . . .
4−20 Initial Bandwith Available Register Description 4−23. . . . . . . . . . . . . . . . . . . . . .
4−21 Initial Channels Available High Register Description 4−23. . . . . . . . . . . . . . . . .
4−22 Initial Channels Available Low Register Description 4−
24. . . . . . . . . . . . . . . . .
4−23 Fairness Control Register Description 4−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−24 Link Control Register Description 4−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−25 Node Identification Register Description 4−26. . . . . . . . . . . . . . . . . . . . . . . . . . .
4−26 PHY Control Register Description 4−27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4−27 Isochronous Cycle Timer Register Description 4−27. . . . . . . . . . . . . . . . . . . . . .
4−28 Asynchronous Request Filter High Register Description 4−28. . . . . . . . . . . . .
4−29 Asynchronous Request Filter Low Register Description 4−30. . . . . . . . . . . . . .
4−30 Physical Request Filter High Register Description 4−31. . . . . . . . . . . . . . . . . . .
4−31 Physical Request Filter Low Register Description 4−33. . . . . . . . . . . . . . . . . . .
4−32 Asynchronous Context Control Register Description 4−34. . . . . . . . . . . . . . . . .
4−33 Asynchronous Context Command Pointer Register Description 4−35. . . . . . .
4−34 Isochronous Transmit Context Control Register Description 4−36. . . . . . . . . .
4−35 Isochronous Receive Context Control Register Description 4−37. . . . . . . . . . .
4−36 Isochronous Receive Context Match Register Description 4−40. . . . . . . . . . . .
5−1 TI Extension Register Map 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5−2 Isochronous Receive Digital Video Enhancements Register Description 5−2
5−3 Link Enhancement Register Description 5−
4. . . . . . . . . . . . . . . . . . . . . . . . . . .
5−4 Timestamp Offset Register Description 5−6. . . . . . . . . . . . . . . . . . . . . . . . . . . .
7−1 Serial EEPROM Map 7−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .