Datasheet

4−24
4.29 Initial Channels Available Low Register
The initial channels available low register value is loaded into the corresponding bus management CSR register on
a system (hardware) or software reset. See Table 4−22 for a complete description of the register contents.
Offset: B8h
Type: Read/Write
Default: FFFF FFFFh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Table 4−22. Initial Channels Available Low Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−0 InitChanAvailLo R/W This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by
a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_LO CSR
register upon a G_RST
, PCI_RST, or a 1394 bus reset.
4.30 Fairness Control Register
The fairness control register provides a mechanism by which software can direct the host controller to transmit
multiple asynchronous requests during a fairness interval. See Table 4−23 for a complete description of the register
contents.
Type: Read-only
Offset: DCh
Default: 0000 0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−23. Fairness Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−8 RSVD R Reserved. Bits 31−8 return 0s when read.
7−0 pri_req R/W This field specifies the maximum number of priority arbitration requests for asynchronous request
packets that the link is permitted to make of the PHY device during a fairness interval.