Datasheet

4−23

4.27 Initial Bandwidth Available Register

The initial bandwidth available register value is loaded into the corresponding bus management CSR register on a

system (hardware) or software reset. See Table 4−20 for a complete description of the register contents.

Type: Read/Write, Read only

Offset: B0h

Default: 0000 1333h

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Default 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1

Table 4−20. Initial Bandwith Available Register Description

BIT FIELD NAME TYPE DESCRIPTION

31−13 RSVD R Reserved. Bits 31−13 return 0s when read.

12−0 InitBWAvailable R/W This field is reset to 1333h on a system (hardware) or software reset, and is not affected by a 1394 bus

reset. The value of this field is loaded into the BANDWIDTH_AVAILABLE CSR register upon a G_RST

PCI_RST

, or a 1394 bus reset.

4.28 Initial Channels Available High Register

The initial channels available high register value is loaded into the corresponding bus management CSR register on

a system (hardware) or software reset. See Table 4−21 for a complete description of the register contents.

Offset: B4h

Type: Read/Write

Default: FFFF FFFFh

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Default 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Table 4−21. Initial Channels Available High Register Description

BIT FIELD NAME TYPE DESCRIPTION

31−0 InitChanAvailHi R/W This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by

a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_HI CSR