Datasheet

4−12
4.16 Host Controller Control Register
The host controller control set/clear register pair provides flags for controlling the TSB82AA2B device. See
Table 4−12 for a complete description of the register contents.
Type: Read/Set/Clear/Update, Read/Set/Clear, Read/Clear, Read only
Offset: 50h set register
54h clear register
Default: X00X 0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 0 X 0 0 0 0 0 0 0 0 0 0 0 X 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−12. Host Controller Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 BIBimageValid RSU When bit 31 is set to 1, the TSB82AA2B physical response unit is enabled to respond to block
read requests to host configuration ROM and to the mechanism for atomically updating
configuration ROM. Software creates a valid image of the bus_info_block in host configuration
ROM before setting this bit.
When this bit is cleared, the TSB82AA2B device returns ack_type_error on block read requests
to host configuration ROM. Also, when this bit is cleared and a 1394 bus reset occurs, the
configuration ROM mapping register at OHCI offset 34h (see Section 4.12, Configuration ROM
Mapping Register), configuration ROM header register at OHCI offset 18h (see Section 4.7,
Configuration ROM Header Register), and bus options register at OHCI offset 20h (see
Section 4.9, Bus Options Register) are not updated.
Software can set this bit only when bit 17 (linkEnable) is 0. Once bit 31 is set to 1, it can be cleared
by a system (hardware) reset, a software reset, or if a fetch error occurs when the TSB82AA2B
device loads bus_info_block registers from host memory.
30 noByteSwapData RSC Bit 30 controls whether physical accesses to locations outside the TSB82AA2B device itself, as
well as any other DMA data accesses, are byte swapped.
29 ack_Tardy_enable RSC Bit 29 controls the acknowledgement of ack_tardy. When bit 29 is set to 1, ack_tardy may be
returned as an acknowledgment to configuration ROM accesses from 1394 to the TSB82AA2B
device, including accesses to the bus_info_block. The TSB82AA2B device returns ack_tardy to
all other asynchronous packets addressed to the TSB82AA2B node. When the TSB82AA2B
device sends ack_tardy, bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h
(see Section 4.21, Interrupt Event Register) is set to 1 to indicate the attempted asynchronous
access.
Software ensures that bit 27 (ack_tardy) in the interrupt event register is 0. Software also unmasks
wake-up interrupt events such as bit 19 (phy) and bit 27 (ack_tardy) in the interrupt event register
before placing the device into D1.
Software does not set this bit if the TSB82AA2B node is the 1394 bus manager.
28−24 RSVD R Reserved. Bits 28−24 return 0s when read.
23 programPhyEnable RC Bit 23 informs upper-level software that lower-level software has consistently configured the IEEE
1394a-2000 enhancements in the link and PHY devices. When this bit is 1, generic software such
as the OHCI driver is responsible for configuring IEEE Std 1394a-2000 enhancements in the PHY
device and bit 22 (aPhyEnhanceEnable) in the TSB82AA2B device. When this bit is 0, the generic
software may not modify the IEEE Std 1394a-2000 enhancements in the TSB82AA2B or PHY
device and cannot interpret the setting of bit 22 (aPhyEnhanceEnable). This bit is initialized from
the serial EEPROM.
22 aPhyEnhanceEnable RSC When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set bit 22 to
1 to use all IEEE Std 1394a-2000 enhancements. When bit 23 (programPhyEnable) is cleared
to 0, the software does not change PHY enhancements or this bit.
21−20 RSVD R Reserved. Bits 21−20 return 0s when read.