Datasheet

4−6
4.6 CSR Control Register
The CSR control register accesses the bus management CSR registers from the host through compare-swap
operations. This register controls the compare-swap operation and selects the CSR resource. See Table 4−5 for a
complete description of the register contents.
Type: Read/Write, Read/Update, Read only
Offset: 14h
Default: 8000 000Xh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X
Table 4−5. CSR Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 csrDone RU Bit 31 is set to 1 by the TSB82AA2B device when a compare-swap operation is complete. It is cleared
whenever this register is written.
30−2 RSVD R Reserved. Bits 30−2 return 0s when read.
1−0 csrSel R/W This field selects the CSR resource as follows:
00 = BUS_MANAGER_ID
01 = BANDWIDTH_AVAILABLE
10 = CHANNELS_AVAILABLE_HI
11 = CHANNELS_AVAILABLE_LO
4.7 Configuration ROM Header Register
The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset
FFFF F000 0400h. See Table 4−6 for a complete description of the register contents.
Type: Read/Write
Offset: 18h
Default: 0000 XXXXh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default X X X X X X X X X X X X X X X X
Table 4−6. Configuration ROM Header Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−24 info_length R/W IEEE Std 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller
control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to
1.
23−16 crc_length R/W IEEE Std 1394 bus-management field. Must be valid when bit 17 (linkEnable) in the host controller
control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to
1.
15−0 rom_crc_value R/W IEEE Std 1394 bus-management field. Must be valid at any time bit 17 (linkEnable) in the host controller
control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to
1. The reset value is undefined if no serial EEPROM is present. If a serial EEPROM is present, this
field is loaded from the serial EEPROM.