Datasheet

4−5
4.3 Asynchronous Transmit Retries Register
The asynchronous transmit retries register indicates the number of times the TSB82AA2B device attempts a retry
for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 4−4
for a complete description of the register contents.
Type: Read/Write, Read only
Offset: 08h
Default: 0000 0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−4. Asynchronous Transmit Retries Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−29 secondLimit R The second limit field returns 0s when read, because outbound dual-phase retry is not
implemented.
28−16 cycleLimit R The cycle limit field returns 0s when read, because outbound dual-phase retry is not implemented.
15−12 RSVD R Reserved. Bits 15−12 return 0s when read.
11−8 maxPhysRespRetries R/W This field tells the physical response unit how many times to attempt to retry the transmit operation
for the response packet when a busy acknowledge or ack_data_error is received from the target
node.
7−4 maxATRespRetries R/W This field tells the asynchronous transmit response unit how many times to attempt to retry the
transmit operation for the response packet when a busy acknowledge or ack_data_error is
received from the target node.
3−0 maxATReqRetries R/W This field tells the asynchronous transmit DMA request unit how many times to attempt to retry the
transmit operation for the response packet when a busy acknowledge or ack_data_error is
received from the target node.
4.4 CSR Data Register
The CSR data register accesses the bus management CSR registers from the host through compare-swap
operations. This register contains the data to be stored in a CSR if the compare is successful.
Type: Read only
Offset: 0Ch
Default: XXXX XXXXh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default X X X X X X X X X X X X X X X X
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default X X X X X X X X X X X X X X X X
4.5 CSR Compare Register
The CSR compare register accesses the bus management CSR registers from the host through compare-swap
operations. This register contains the data to be compared with the existing value of the CSR resource.
Type: Read only
Offset: 10h
Default: XXXX XXXXh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default X X X X X X X X X X X X X X X X
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default X X X X X X X X X X X X X X X X