Datasheet

3−20
3.26 GPIO Control Register
The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See Table 3−24 for a
complete description of the register contents.
Type: Read/Write/Update, Read/Write, Read only
Offset: FCh
Default: 0000 0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 3−24. GPIO Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−24 RSVD R Reserved. Bits 31−24 return 0s when read.
23 INT_EN R/W When bit 23 is set to 1, a TSB82AA2B general-purpose interrupt event occurs on a level change of the
GPIO input. This event may generate an interrupt, with mask and event status reported through the
interrupt mask register at OHCI offset 88h/8Ch (see Section 4.22, Interrupt Mask Register) and the
interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register).
22 RSVD R Reserved. Bit 22 returns 0 when read.
21 GPIO_INV R/W GPIO polarity invert. When bit 21 is set to 1, the polarity of GPIO is inverted.
20 GPIO_ENB R/W GPIO enable control. When bit 20 is set to 1, the output is enabled. Otherwise, the output is high
impedance.
19−17 RSVD R Reserved. Bits 19−17 return 0s when read.
16 GPIO_DATA RWU GPIO data. Reads from bit 16 return the logical value of the input to GPIO. Writes to this bit update the
value to drive to GPIO when the output is enabled.
15−0 RSVD R Reserved. Bits 15−0 return 0s when read.