Datasheet

3−19
Table 3−22. Link Enhancement Control Register Description (Continued)
BIT FIELD NAME TYPE DESCRIPTION
5−3 RSVD R Reserved. Bits 5−3 return 0s when read.
2 enab_insert_idle R/W Enable insert idle (OHCI-Lynx compatible). When the PHY device has control of the
PHY_CTL0−PHY_CTL1 control lines and PHY_DATA0−PHY_DATA7 data lines and the link requests
control, the PHY device drives 11b on the PHY_CTL0−PHY_CTL1 lines. The link can then start driving
these lines immediately. Setting bit 2 to 1 inserts an idle state, so the link waits one clock cycle before
it starts driving the lines (turnaround time).
1 enab_accel R/W Enable acceleration enhancements (OHCI-Lynx compatible). When bit 1 is set to 1, the PHY device
is notified that the link supports the IEEE Std 1394a-2000 acceleration enhancements, that is,
ack-accelerated, fly-by concatenation, etc. It is recommended that bit 1 be set to 1.
0 RSVD R Reserved. Bit 0 returns 0 when read.
3.25 Subsystem Access Registers
Write access to the subsystem access registers updates the subsystem ID registers identically to OHCI-Lynx
controller. The system ID value written to these registers may also be read back from these registers. See Table 3−23
for a complete description of the register contents.
Type: Read/Write
Offset: F8h
Default: 0000 0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 3−23. Subsystem Access Registers Description
BIT FIELD NAME TYPE DESCRIPTION
31−16 SUBDEV_ID R/W Subsystem device ID alias. This field indicates the subsystem device ID.
15−0 SUBVEN_ID R/W Subsystem vendor ID alias. This field indicates the subsystem vendor ID.