Datasheet

3−18
3.24 Link Enhancement Control Register
The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial
EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22 (aPhyEnhanceEnable)
in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is
set to 1. See Table 3−22 for a complete description of the register contents.
Type: Read/Write, Read only
Offset: F4h
Default: 0000 0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 3−22. Link Enhancement Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−16 RSVD R Reserved. Bits 31−16 return 0s when read.
15 DisableATPipelining R/W Disable AT pipelining. When bit 15 is set to 1, out-of-order AT pipelining is disabled.
14 EnableDraft R/W Enable OHCI 1.2 draft features. When bit 14 is set to 1, it enables some features beyond the OHCI
1.1 specification. Specifically, this enables HCControl.LPS to be cleared by writing a 1 to the
HCControlClear.LPS bit and enables the link to set bit 9 in the xferStatus field of AR and IR
ContextControl registers.
13−12 atx_thresh R/W This field sets the initial AT threshold value, which is used until the AT FIFO is underrun. When the
TSB82AA2B device retries the packet, it uses a 2K-byte threshold resulting in a store-and-forward
operation.
00 = Threshold ~4K bytes resulting in a store-and-forward operation (default)
01 = Threshold ~1.7K bytes
10 = Threshold ~1K bytes
11 = Threshold ~512 bytes
These bits fine tune the asynchronous transmit threshold. Changing this value may increase or
decrease the 1394 latency depending on the average PCI bus latency.
Setting the AT threshold to 1.7K, 1K, or 512 bytes results in data being transmitted at these
thresholds or when an entire packet has been checked into the FIFO. If the packet to be transmitted
is larger than the AT threshold, the remaining data must be received before the AT FIFO is emptied;
otherwise, an underrun condition occurs, resulting in a packet error at the receiving node. As a result,
the link then commences store-and-forward operation—that is, wait until it has the complete packet
in the FIFO before retransmitting it on the second attempt, to ensure delivery.
An AT threshold of 4K results in store-and-forward operation, which means that asynchronous data
is not transmitted until an end-of-packet token is received. Restated, setting the AT threshold to 4K
results in only complete packets being transmitted.
Note that this device always uses store-and-forward when the asynchronous transmit retries
register at OHCI offset 08h (see Section 4.3, Asynchronous Transmit Retries Register) is cleared.
11−10 RSVD R Reserved. Bits 11−10 return 0s when read.
9 enab_aud_ts R/W Enable audio/music CIP timestamp enhancement. When bit 9 is set to 1, the enhancement is
enabled for audio/music CIP transmit streams (FMT = 10h).
8 enab_dv_ts R/W Enable DV CIP timestamp enhancement. When bit 8 is set to 1, the enhancement is enabled for DV
CIP transmit streams (FMT = 00h).
7 enab_unfair R/W Enable asynchronous priority requests (OHCI-Lynx compatible). Setting bit 7 to 1 enables the link
to respond to requests with priority arbitration. It is recommended that this bit be set to 1.
6 RSVD R Bit 6 is not assigned in the TSB82AA2B follow-on products since this location, which is loaded by
the serial EEPROM from the enhancements field, corresponds to bit 23 (programPhyEnable) in the
host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control
Register).