Datasheet

3−15
3.20 Power Management Control and Status Register
The power management control and status register implements the control and status of the PCI power management
function. This register is not affected by the internally generated reset caused by the transition from the D3
hot
to D0
state. See Table 3−18 for a complete description of the register contents.
Type: Read/Clear, Read/Write, Read only
Offset: 48h
Default: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 3−18. Power Management Control and Status Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 PME_STS RC Bit 15 is set to 1 when the TSB82AA2B device normally asserts the PME signal, independent of the
state of bit 8 (PME_ENB). This bit is cleared by a writeback of 1, which also clears the PCI_PME
signal
driven by the TSB82AA2B device. Writing a 0 to this bit has no effect.
14−9 RSVD R Reserved. Bits 14−9 return 0s when read.
8 PME_ENB R/W When bit 8 is set to 1, PME assertion is enabled. When bit 8 is cleared, PME assertion is disabled. This
bit defaults to 0 if the function does not support PME
generation from D3
cold
. If the function supports
PME
from D3
cold
, then this bit is sticky and must be explicitly cleared by the operating system each time
it is initially loaded. Functions that do not support PME
generation from any D-state[(that is, bits 15−11
in the power management capabilities register at offset 46h in the PCI configuration space (see
Section 3.19, Power Management Capabilities Register) equal 00000b], may hardwire this bit to be
read only, always returning a 0 when read by system software.
7−2 RSVD R Reserved. Bits 7−2 return 0s when read.
1−0 PWR_STATE R/W Power state. This 2-bit field is used to set the TSB82AA2B device power state and is encoded as
follows:
00 = Current power state is D0.
01 = Current power state is D1.
10 = Current power state is D2.
11 = Current power state is D3.
3.21 Power Management Extension Register
The power management extension register provides extended power-management features not applicable to the
TSB82AA2B device; thus, it is read only and returns 0s when read. See Table 3−19 for a complete description of the
register contents.
Type: Read only
Offset: 4Ah
Default: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 3−19. Power Management Extension Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−0 RSVD R Reserved. Bits 15−0 return 0s when read.