Datasheet

3−13
3.17 OHCI Control Register
The OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for
big endian PCI support. See Table 3−15 for a complete description of the register contents.
Type: Read/Write
Offset: 40h
Default: 0000 0000h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 3−15. OHCI Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−1 RSVD R Reserved. Bits 31−1 return 0s when read.
0 GLOBAL_SWAP R/W When bit 0 is set to 1, all quadlets read from and written to the PCI interface are byte swapped (big
endian). This bit is loaded from serial EEPROM and must be cleared to 0 for normal operation.
3.18 Capability ID and Next Item Pointer Register
The capability ID and next item pointer register identifies the linked-list capability item and provides a pointer to the
next capability item, respectively. See Table 3−16 for a complete description of the register contents.
Type: Read only
Offset: 44h
Default: 0001h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Table 3−16. Capability ID and Next Item Pointer Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 NEXT_ITEM R Next item pointer. The TSB82AA2B device supports only one additional capability that is
communicated to the system through the extended capabilities list; therefore, this field returns 00h
when read.
7−0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI
SIG for PCI power-management capability.