Datasheet

3−12
3.15 Interrupt Line and Interrupt Pin Registers
The interrupt line and interrupt pin registers communicate interrupt line routing information. See Table 3−13 for a
complete description of the register contents.
Type: Read/Write, Read only
Offset: 3Ch
Default: 0100h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0
Table 3−13. Interrupt Line and Interrupt Pin Registers Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 INTR_PIN R Interrupt pin. Returns 01h when read, indicating that the TSB82AA2B PCI function signals interrupts on
the PCI_INTA
terminal.
7−0 INTR_LINE R/W Interrupt line. This field is programmed by the system and indicates to software which interrupt line the
TSB82AA2B PCI_INTA
is connected to.
3.16 Minimum Grant and Maximum Latency Registers
The minimum grant and maximum latency registers communicate to the system the desired setting of bits 15−8 in
the latency timer and class cache line size register at offset 0Ch in the PCI configuration space (see Section 3.7,
Latency Timer and Class Cache Line Size Register). If a serial EEPROM is detected, the contents of these registers
are loaded through the serial EEPROM interface after a PCI_RST
. If no serial EEPROM is detected, these registers
return a default value that corresponds to the MIN_GNT = 2, MAX_LAT = 4. See Table 3−14 for a complete description
of the register contents.
Type: Read/Update
Offset: 3Eh
Default: 0402h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0
Table 3−14. Minimum Grant and Maximum Latency Registers Description
BIT FIELD NAME TYPE DESCRIPTION
15−8 MAX_LAT RU Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level
to the TSB82AA2B device. The default for this field indicates that the TSB82AA2B device may need to
access the PCI bus as often as every 0.25 μs; thus, an extremely high priority level is requested. The
contents of this field may also be loaded through the serial EEPROM.
7−0 MIN_GNT RU Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value
to the TSB82AA2B device. The default for this field indicates that the TSB82AA2B device may need to
sustain burst transfers for nearly 64 μs and, thus, request a large value be programmed in bits 15−8 of the
TSB82AA2B latency timer and class cache line size register at offset 0Ch in the PCI configuration space
(see Section 3.7, Latency Timer and Class Cache Line Size Register).