Datasheet

3−10
3.12 CardBus CIS Pointer Register
The TSB82AA2B device may be configured to support CardBus registers via bit 6 (CARDBUS) in the PCI
miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.23, Miscellaneous
Configuration Register). If CARDBUS is low (default), this register is read-only returning 0s when read. If CARDBUS
is high, this register contains the pointer to the CardBus card information structure (CIS). See Table 3−11 for a
complete description of the register contents.
Type: Read only
Offset: 28h
Default: 0000 000Xh
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X
Table 3−11. CardBus CIS Pointer Register Description
BIT FIELD NAME TYPE DESCRIPTION
31−28 ROM_IMAGE R Since the CIS is not implemented as a ROM image, this field returns 0s when read.
27−3 CIS_OFFSET R This field indicates the offset into the CIS address space where the CIS begins, and bits 7−3 are loaded
from the serial EEPROM field CIS_Offset (7−3). This implementation allows the TSB82AA2B device to
produce serial EEPROM addresses equal to the lower PCI address byte to acquire data from the serial
EEPROM.
2−0 CIS_INDICATOR R This field indicates the address space where the CIS resides and returns 011b if bit 6 (CARDBUS) in
the PCI miscellaneous configuration register is high, 011b indicates that CardBus CIS base address
register at offset 18h in the PCI configuration header contains the CIS base address. If CARDBUS is
low, this field returns 000b when read.