Datasheet

3−4
3.3 Device ID Register
The device ID register contains a value assigned to the TSB82AA2B device by TI. The device ID for the TSB82AA2B
device is 8025h.
Type: Read only
Offset: 02h
Default: 8025h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1
3.4 Command Register
The command register provides control over the TSB82AA2B interface to the PCI bus. All bit functions adhere to the
definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 3−3 for a complete
description of the register contents.
Type: Read/Write, Read only
Offset: 04h
Default: 0000h
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 3−3. Command Register Description
BIT FIELD NAME TYPE DESCRIPTION
15−11 RSVD R Reserved. Bits 15−11 return 0s when read.
10 INT_DISABLE R/W INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.
0 = INTx
assertion is enabled (default).
1 = INTx
assertion is disabled.
This bit has been defined as part of the PCI Local Bus Specification (Revision 2.3).
9 FBB_ENB R Fast back-to-back enable. The TSB82AA2B device does not generate fast back-to-back transactions;
therefore, bit 9 returns 0 when read.
8 SERR_ENB R/W PCI_SERR enable. When bit 8 is set to 1, the TSB82AA2B PCI_SERR driver is enabled. PCI_SERR
can be asserted after detecting an address parity error on the PCI bus.
7 STEP_ENB R Address/data stepping control. The TSB82AA2B device does not support address/data stepping;
therefore, bit 7 is hardwired to 0.
6 PERR_ENB R/W Parity error enable. When bit 6 is set to 1, the TSB82AA2B device is enabled to drive PCI_PERR
response to parity errors through the PCI_PERR signal.
5 VGA_ENB R VGA palette snoop enable. The TSB82AA2B device does not feature VGA palette snooping; therefore,
bit 5 returns 0 when read.
4 MWI_ENB R/W Memory write and invalidate enable. When bit 4 is set to 1, the TSB82AA2B device is enabled to
generate MWI PCI bus commands. If this bit is cleared, the TSB82AA2B device generates memory
write commands instead.
3 SPECIAL R Special cycle enable. The TSB82AA2B function does not respond to special cycle transactions;
therefore, bit 3 returns 0 when read.
2 MASTER_ENB R/W Bus master enable. When bit 2 is set to 1, the TSB82AA2B device is enabled to initiate cycles on the
PCI bus.
1 MEMORY_ENB R/W Memory response enable. Setting bit 1 to 1 enables the TSB82AA2B device to respond to memory
cycles on the PCI bus. This bit must be set to access OHCI registers.
0 IO_ENB R I/O space enable. The TSB82AA2B device does not implement any I/O-mapped functionality;
therefore, bit 0 returns 0 when read.