Datasheet

3−3
3.1 PCI Configuration Registers
The TSB82AA2B device is a single-function PCI device. The configuration header is compliant with the PCI Local
Bus Specification as a standard header. Table 3−2 illustrates the PCI configuration header that includes both the
predefined portion of the configuration space and the user-definable registers.
Table 3−2. PCI Configuration Register Map
REGISTER NAME OFFSET
Device ID Vendor ID 00h
Status Command 04h
Class code Revision ID 08h
BIST Header type Latency timer Cache line size 0Ch
OHCI base address 10h
TI extension base address 14h
CardBus CIS base address 18h
Reserved 1Ch−27h
CardBus CIS pointer 28h
Subsystem ID Subsystem vendor ID 2Ch
Reserved 30h
Reserved
Power management
capabilities pointer
34h
Reserved 38h
Maximum latency Minimum grant Interrupt pin Interrupt line 3Ch
OHCI control 40h
Power management capabilities Next item pointer Capability ID 44h
Multifunction select
Power management
extension
Power management control and status 48h
Reserved 4Ch−ECh
Miscellaneous configuration F0h
Link enhancement control F4h
Subsystem device ID alias Subsystem vendor ID alias F8h
GPI control Reserved FCh
3.2 Vendor ID Register
The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.
The vendor ID assigned to TI is 104Ch.
Type: Read only
Offset: 00h
Default: 104Ch
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0