Datasheet

3−2
Internal
Registers
ISO Transmit
Contexts
Async Transmit
Contexts
Physical DMA
and Response
PCI
Target
SM
PHY
Register
Access
& Status
Monitor
Central
Arbiter
and
PCI
Initiator
SM
Cycle Start
Generator and
Cycle Monitor
Synthesized
Bus Reset
Receive
FIFO
Link
Transmit
Link
Receive
PCI
Host
Bus
Interface
Response
Timeout
Request
Filters
General
Request Receive
Async Response
Receive
ISO Receive
Contexts
OHCI PCI Power
Mgmt and CLKRUN
Transmit
FIFO
Receive
Acknowledge
Serial
ROM
GPIOs
CRC
PHY /
Link
Interface
Misc
Interface
Figure 3−1. TSB82AA2B Block Diagram