Datasheet

2−11
Table 2−8. PHY-Link Interface Terminals
TERMINAL
NAME
NUMBER
I/O DESCRIPTION
NAME
PGE GGW
I/O
DESCRIPTION
PHY_CTL1
PHY_CTL0
133
134
A07
B07
I/O
PHY-link interface control. These bidirectional control bus signals indicate the phase of operation of
the PHY-link interface. Upon a reset of the interface, this bus is driven by the PHY. When driven by the
PHY, information on PHY_CTL0 and PHY_CTL1 is synchronous to PHY_PCLK. When driven by the
link, information on PHY_CTL0 and PHY_CTL1 is synchronous to PHY_LCLK.
PHY_D7
PHY_D6
PHY_D5
PHY_D4
PHY_D3
PHY_D2
PHY_D1
PHY_D0
123
124
125
128
129
130
131
132
D10
C10
B10
C09
B09
A08
B08
D08
I/O
PHY-link interface data. These bidirectional data bus signals carry 1394 packet data, packet speed,
and grant type information between the PHY and the link. Upon a reset of the interface, this bus is
driven by the PHY. When driven by the PHY, information on PHY_D7 through PHY_D0 is synchronous
to PHY_PCLK. When driven by the link, information on PHY_D7 through PHY_D0 is synchronous to
PHY_LCLK.
PHY_LINKON 142 C04 I/O
Link-on notification. PHY_LINKON is an input to the TSB82AA2B device from the PHY that is used
to provide notification that a link-on packet has been received, or, if the PHY is configured properly,
an event such as a port connection has occurred. This input only has meaning when LPS is disabled.
This includes the D0 (uninitialized), D2, and D3 power states. If PHY_LINKON becomes active in the
D0 (uninitialized), D2, or D3 power state, the TSB82AA2B device sets bit 15 (PME_STS) in the power
management control and status register in the PCI configuration space at offset 48h (see Section 3.20,
Power Management Control and Status Register).
PHY_LPS 144 B03 I/O
Link power status. PHY_LPS is an output from the TSB82AA2B device that, when active, indicates
that the link is powered and capable of maintaining communications over the PHY-link interface. When
this signal is inactive, it indicates that the link is not powered or that the link has not been initialized by
software. This signal is active when bit 19 (LPS) in the host controller control register at OHCI offset
50h/54h (see Section 4.16, Host Controller Control Register) has been set by software according to
the initialization as specified in the 1394 Open Host Controller Interface specification. When active, the
signal is nominally a 2-MHz pulse.
PHY_LREQ 141 B04 O
Link request. PHY_LREQ is a serial output from the TSB82AA2B device to the PHY used to request
packet transmissions, read and write PHY registers, and to indicate the occurrence of certain link
events that are relevant to the PHY. Information encoded on PHY_LREQ is synchronous to
PHY_LCLK.
PHY_LCLK 136 A06 O
Link clock. PHY_LCLK is an output from the TSB82AA2B device that is generated from the incoming
PHY_PCLK signal. PHY_LCLK is freqency-locked to PHY_PCLK and synchronizes data and
information generated by the link.
PHY_PCLK 138 A05 I
PHY clock. PHY_PCLK is an input to the TSB82AA2B device from the PHY that, when active, provides
a nominal 98.304-MHz clock with a nominal 50% duty cycle.
PHY_PINT 143 A03 I
PHY interrupt. PHY_PINT is a serial input to the TSB82AA2B device from the PHY that is used to
transfer status, register, interrupt, and other information to the link. Information encoded on PHY_PINT
is synchronous to PHY_PCLK.