Datasheet

2−10
Table 2−7. PCI 64-Bit Bus Extension Terminals
TERMINAL
NAME
NO.
I/O DESCRIPTION
NAME
PGE GGW
I/O
DESCRIPTION
PCI_ACK64 72 U16 I
PCI bus 64-bit transfer acknowledge. Asserted by a target if it is willing to accept a 64-bit data transfer
when it positively decodes its address for a memory transaction and the master has requested a 64-bit
data transfer by asserting PCI_REQ64. PCI_REQ64 has identical timing to PCI_DEVSEL. When the
TSB82AA2B device is bus master, it monitors PCI_REQ64
when it has requested a 64-bit data transfer
for the current transaction. If the target asserts PCI_REQ64
when it claims the cycle, the TSB82AA2B
device transfers data using 64 bits. As a target, the TSB82AA2B does not support 64-bit data transfers
and never asserts PCI_REQ64
when another master has requested 64-bit transfer.
PCI_AD63
PCI_AD62
PCI_AD61
PCI_AD60
PCI_AD59
PCI_AD58
PCI_AD57
PCI_AD56
PCI_AD55
PCI_AD54
PCI_AD53
PCI_AD52
PCI_AD51
PCI_AD50
PCI_AD49
PCI_AD48
PCI_AD47
PCI_AD46
PCI_AD45
PCI_AD44
PCI_AD43
PCI_AD42
PCI_AD41
PCI_AD40
PCI_AD39
PCI_AD38
PCI_AD37
PCI_AD36
PCI_AD35
PCI_AD34
PCI_AD33
PCI_AD32
82
83
84
85
88
89
90
92
94
95
96
97
98
99
100
101
104
105
106
107
108
109
110
111
113
114
115
116
118
119
120
121
L15
L16
L17
K17
K16
J17
J14
H16
H15
G17
G16
G15
G14
F17
F16
F15
D17
D16
D15
C17
C16
C14
B14
A14
B13
A13
C12
B12
D11
C11
B11
A11
I/O
PCI address/data bus for the upper DWORD. These signals make up the multiplexed PCI address and
data bus for the upper 32 bits of the PCI interface. During the address phase of a dual address command
with PCI_REQ64 asserted, AD63−AD32 contain the upper 32 bits of a 64-bit address. During the data
phase, AD63−AD32 contain data when a 64-bit transfer has been negotiated by the assertion of
PCI_REQ64
by the master and PCI_ACK64 by the target. Note, the TSB82AA2B does not support the
dual address command.
PCI_C/BE7
PCI_C/BE6
PCI_C/BE5
PCI_C/BE4
74
77
78
79
R17
N16
N17
M15
I/O
PCI bus commands and byte enables for the upper DWORD. During the address phase of a bus cycle,
PCI_C/BE7
−PCI_C/BE4 are reserved and indeterminate since the TSB82AA2B does not support the
dual address command. During the data phase, this 4-bit bus is used as a byte enable for the upper 32
bits when a 64-bit transfer has been negotiated by the assertion of PCI_REQ64 by the master and
PCI_ACK64
by the target.
PCI_PAR64 80 M17 I
PCI parity for the upper DWORD. In all PCI bus read and write cycles, the TSB82AA2B device calculates
even parity across the PCI_AD63−PCI_AD32 and PCI_C/BE4
−PCI_C/BE7 buses. As an initiator during
PCI cycles, the TSB82AA2B device outputs this parity indicator with a one-PCI_CLK delay. As a target
during PCI cycles, the calculated parity is compared to the initiator parity indicator; a miscompare can
result in a parity error assertion (PCI_PERR
).
PCI_REQ64 73 R16 I
PCI bus request for 64-bit transfer. Asserted by a bus master to request a 64-bit transfer for a memory
transaction. The timing of PCI_REQ64
is identical to PCI_FRAME. When the TSB82AA2B device is the
bus master, it asserts PCI_REQ64
to request a 64-bit transfer on the current transaction. The
TSB82AA2B device only requests a 64-bit transfer for a memory transaction. The target asserts
PCI_ACK64
if it is willing to transfer data using 64 bits.