Datasheet

2−9
Table 2−6. 32-Bit PCI Bus Terminals (Continued)
TERMINAL
NAME
NO.
I/O DESCRIPTION
NAME
PGE GGW
I/O
DESCRIPTION
PCI_IRDY 41 U04 I/O
PCI initiator ready. PCI_IRDY indicates the ability of the PCI bus initiator to complete the current data
phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both
PCI_IRDY and PCI_TRDY are asserted.
PCI_PAR 49 U08 I/O
PCI parity. In all PCI bus read and write cycles, the TSB82AA2B device calculates even parity across
the PCI_AD31−PCI_AD0 and PCI_C/BE0
−PCI_C/BE3 buses. As an initiator during PCI cycles, the
TSB82AA2B device outputs this parity indicator with a one-PCI_CLK delay. As a target during PCI
cycles, the calculated parity is compared to the initiator parity indicator; a miscompare can result in a
parity error assertion (PCI_PERR
).
PCI_PERR 47 T07 I/O
PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does
not match PCI_PAR and/or PCI_PAR64 when PERR_ENB (bit 6) is set to 1 in the command register
at offset 04h in the PCI configuration space (see Section 3.4, Command Register).
PCI_PME 14 H01 O
This terminal indicates wake events to the host. It is an open-drain signal which is asserted when
PME_STS is asserted and bit 8 (PME_ENB) in the PCI power management control and status register
at offset 48h in the PCI configuration space (see Section 3.20, Power Management Control and Status
Register) has been set. Bit 15 (PME_STS) in the PCI power management control and status register
is set due to any unmasked interrupt in the D0 (active) or D1 power state, and on a PHY_LINKON
indication in the D2, D3, or D0 (uninitialized) power state.
PCI_REQ 13 G01 O
PCI bus request. Asserted by the TSB82AA2B device to request access to the bus as an initiator. The
host arbiter asserts PCI_GNT
when the TSB82AA2B device has been granted access to the bus.
PCI_SERR 48 U07 O
PCI system error. When SERR_ENB (bit 8) in the command register at offset 04h in the PCI
configuration space (see Section 3.4, Command Register) is set to 1, the output is pulsed, indicating
an address parity error has occurred. The TSB82AA2B device need not be the target of the PCI cycle
to assert this signal. This terminal is implemented as open-drain.
PCI_STOP 46 P07 I/O
PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current
PCI bus transaction. This signal is used for target disconnects, and is commonly asserted by target
devices which do not support burst data transfers.
PCI_TRDY 44 T06 I/O
PCI target ready. PCI_TRDY indicates the ability of the PCI bus target to complete the current data
phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both
PCI_IRDY and PCI_TRDY are asserted.