Datasheet
2−8
Table 2−6. 32-Bit PCI Bus Terminals
TERMINAL
NAME
NO.
I/O DESCRIPTION
NAME
PGE GGW
I/O
DESCRIPTION
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0
17
18
19
20
23
24
25
26
29
30
33
34
35
36
37
38
51
53
54
56
57
58
59
60
64
65
66
67
68
69
70
71
H02
J01
J04
J02
K03
L01
L02
L03
M02
M03
P01
P02
P03
R01
T03
U03
U09
R09
T09
T10
P10
R10
U11
T11
U13
T13
R13
U14
T14
R14
U15
T15
I/O
PCI address/data bus for the lower DWORD. These signals make up the multiplexed PCI address and
data bus for the lower 32 bits on the PCI interface. During the address phase of a PCI cycle, AD31−AD0
contain a 32-bit address or other destination information. During the data phase, AD31−AD0 contain
data.
PCI_C/BE0
PCI_C/BE1
PCI_C/BE2
PCI_C/BE3
61
50
39
27
R11
P08
R04
L04
I/O
PCI bus commands and byte enables for lower DWORD. The command and byte enable signals are
multiplexed on the same PCI terminals. During the address phase of a bus cycle,
PCI_C/BE3−PCI_C/BE0 define the bus command. During the data phase, this 4-bit bus is used as a
byte enable for the lower 32 bits of data.
PCI_CLK 10 G03 I
PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at the
rising edge of PCI_CLK.
PCI_DEVSEL 45 U06 I/O
PCI device select. The TSB82AA2B device asserts this signal to claim a PCI cycle as the target device.
As a PCI initiator, the TSB82AA2B device monitors this signal until a target responds. If no target
responds before time-out occurs, the TSB82AA2B device terminates the cycle with an initiator abort.
PCI_FRAME 40 T04 I/O
PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. PCI_FRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted.
When PCI_FRAME is deasserted, the PCI bus transaction is in the final data phase.
PCI_GNT 12 G02 I
PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB82AA2B device access to
the PCI bus after the current data transaction has completed. This signal may or may not follow a PCI
bus request, depending upon the PCI bus parking algorithm.
PCI_IDSEL 28 M01 I
Initialization device select. PCI_IDSEL selects the TSB82AA2B device during configuration space
accesses. PCI_IDSEL can be connected to 1 of the upper 24 PCI address lines on the PCI bus.
PCI_INTA 5 E03 O
Interrupt signal. This output indicates interrupts from the TSB82AA2B device to the host. This terminal
is implemented as open-drain.