TSB82AA2B 1394b OHCI-Lynxt Controller Data Manual October 2011 Connectivity Solutions SCPS172A
Contents Section 1 2 3 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Trademarks . . . . .
Section 4 iv Title OHCI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 OHCI Version Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 GUID ROM Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.3 Asynchronous Transmit Retries Register . . . . . . . . . . . . . . . . . . . . . . . 4.4 CSR Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
Section 5 6 7 8 9 Title 4.42 Isochronous Transmit Context Control Register . . . . . . . . . . . . . . . . . . 4.43 Isochronous Transmit Context Command Pointer Register . . . . . . . . 4.44 Isochronous Receive Context Control Register . . . . . . . . . . . . . . . . . . 4.45 Isochronous Receive Context Command Pointer Register . . . . . . . . 4.46 Isochronous Receive Context Match Register . . . . . . . . . . . . . . . . . . . TI Extension Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations Figure 2−1 2−2 3−1 6−1 vi Title Page PGE-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1 GGW-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 TSB82AA2B Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2 GPIO Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 3−12 3−13 3−14 3−15 3−16 3−17 3−18 3−19 3−20 3−21 3−22 3−23 3−24 4−1 4−2 4−3 4−4 4−5 Title Signal Names Sorted by PGE Terminal Numbers . . . . . . . . . . . . . . . . . . . Signal Names Sorted by GGW Terminal Numbers . . . . . . . . . . . . . . . . . . . Signal Names Sorted Alphanumerically to Terminal Number . . . . . . . . . . Power Supply Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4−6 4−7 4−8 4−9 4−10 4−11 4−12 4−13 4−14 4−15 4−16 4−17 4−18 4−19 4−20 4−21 4−22 4−23 4−24 4−25 4−26 4−27 4−28 4−29 4−30 4−31 4−32 4−33 4−34 4−35 4−36 5−1 5−2 5−3 5−4 7−1 viii Title Configuration ROM Header Register Description . . . . . . . . . . . . . . . . . . . . Bus Options Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration ROM Mapping Register Description . . . . . . . . . . . . . . . . . . . Posted Write Address Low Register Description . . .
1 Introduction This chapter provides an overview of the Texas Instruments TSB82AA2B device and its features. 1.1 Description The TSB82AA2B OHCI-Lynx™ controller is a discrete 1394b link-layer device, which has been designed to meet the demanding requirements of today’s 1394 bus designs. The TSB82AA2B device is capable of exceptional 800M bit/s performance; thus, providing the throughput and bandwidth to move data efficiently and quickly between the PCI and 1394 buses.
One of the key elements for reducing the TSB82AA2B operational power requirements is the TI advanced CMOS process and the implementation of an internal 1.8-V core, which is supplied by an improved integrated 3.3-V to 1.8-V voltage regulator. The TSB82AA2B implements a next-generation voltage regulator that is more efficient than its predecessors, thus providing an overall reduction in the device operational power requirements especially when operating in D3cold using auxiliary power.
1.3 Related Documents • 1394 Open Host Controller Interface Specification (Revision 1.2) • IEEE Standard for a High-Performance Serial Bus (IEEE Std 1394-1995) • IEEE Standard for a High-Performance Serial Bus — Amendment 1 (IEEE Std 1394a-2000) • P1394b Draft Standard for High-Performance Serial Bus (Supplement) • PC 2001 Design Guide • PCI Bus Power-Management Interface Specification (Revision 1.1) • PCI Local Bus Specification (Revision 2.
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2 Terminal Descriptions 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 PCI_AD43 PCI_AD44 PCI_AD45 PCI_AD46 PCI_AD47 GND VCC PCI_AD48 PCI_AD49 PCI_AD50 PCI_AD51 PCI_AD52 PCI_AD53 PCI_AD54 PCI_AD55 GND PCI_AD56 VCCP PCI_AD57 PCI_AD58 PCI_AD59 REG18 V CC PCI_AD60 PCI_AD61 PCI_AD62 PCI_AD63 GND PCI_PAR64 PCI_C/BE4 PCI_C/BE5 PCI_C/BE6 GND VCC PCI_C/BE7 PCI_REQ64 This section provides the terminal descriptions for the TSB82AA2B device.
1 U 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 NC PCI_ AD16 PCI_ IRDY NC PCI_ DEVSEL PCI_ SERR PCI_ PAR PCI_ AD15 VCCP PCI_ AD9 NC PCI_ AD7 PCI_ AD4 PCI_ AD1 PCI_ ACK64 PCI_ AD17 PCI_ FRAME NC PCI_ TRDY PCI_ PERR NC PCI_ AD13 PCI_ AD12 PCI_ AD8 NC PCI_ AD6 PCI_ AD3 PCI_ AD0 PCI_ C/BE2 VCC GND NC NC PCI_ AD14 PCI_ AD10 PCI_ C/BE0 GND PCI_ AD5 PCI_ AD2 PCI_ STOP PCI_ C/BE1 GND PCI_ AD11 VCC T NC R PCI_ AD18 NC P PCI_ AD21 PCI_ AD20 PCI_ AD19 N VC
Table 2−1. Signal Names Sorted by PGE Terminal Numbers NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO.
Table 2−2. Signal Names Sorted by GGW Terminal Numbers TERMINAL NO. SIGNAL NAME TERMINAL NO. SIGNAL NAME TERMINAL NO. SIGNAL NAME TERMINAL NO.
Table 2−3.
Table 2−3.
Table 2−5. Reset and Miscellaneous Terminals TERMINAL NAME G_RST NO. PGE 7 I/O DESCRIPTION I Global power reset. This reset brings all of the TSB82AA2B internal registers to their default states, including those registers not reset by PCI_RST. When G_RST is asserted, the device is completely nonfunctional. Additionally, G_RST must be asserted a minimum of 2 ms after both 3.3 V and 1.8 V are valid at the device.
Table 2−6. 32-Bit PCI Bus Terminals TERMINAL NO. I/O DESCRIPTION I/O PCI address/data bus for the lower DWORD. These signals make up the multiplexed PCI address and data bus for the lower 32 bits on the PCI interface. During the address phase of a PCI cycle, AD31−AD0 contain a 32-bit address or other destination information. During the data phase, AD31−AD0 contain data. R11 P08 R04 L04 I/O PCI bus commands and byte enables for lower DWORD.
Table 2−6. 32-Bit PCI Bus Terminals (Continued) TERMINAL NAME PCI_IRDY NO. PGE GGW 41 U04 I/O DESCRIPTION I/O PCI initiator ready. PCI_IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY and PCI_TRDY are asserted. PCI_PAR 49 U08 I/O PCI parity.
Table 2−7. PCI 64-Bit Bus Extension Terminals TERMINAL NAME NO.
Table 2−8. PHY-Link Interface Terminals TERMINAL NAME NUMBER PGE GGW PHY_CTL1 133 A07 PHY_CTL0 134 B07 PHY_D7 PHY_D6 PHY_D5 PHY_D4 PHY_D3 PHY_D2 PHY_D1 PHY_D0 123 124 125 128 129 130 131 132 D10 C10 B10 C09 B09 A08 B08 D08 PHY_LINKON PHY_LPS 142 144 C04 B03 I/O DESCRIPTION I/O PHY-link interface control. These bidirectional control bus signals indicate the phase of operation of the PHY-link interface. Upon a reset of the interface, this bus is driven by the PHY.
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3 TSB82AA2B Controller Programming Model This section describes the internal PCI configuration registers used to program the TSB82AA2B device. All registers are detailed in the same format − a brief description for each register, followed by the register offset and a bit table describing the reset state for each register.
PCI Target SM Internal Registers Serial ROM OHCI PCI Power Mgmt and CLKRUN GPIOs Misc Interface ISO Transmit Contexts Async Transmit Contexts Transmit FIFO Physical DMA and Response Response Timeout PCI Host Bus Interface Central Arbiter and PCI Initiator SM PHY Register Access & Status Monitor Request Filters Link Transmit Receive Acknowledge Cycle Start Generator and Cycle Monitor Link Receive Receive FIFO ISO Receive Contexts Figure 3−1.
3.1 PCI Configuration Registers The TSB82AA2B device is a single-function PCI device. The configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 3−2 illustrates the PCI configuration header that includes both the predefined portion of the configuration space and the user-definable registers. Table 3−2.
3.3 Device ID Register The device ID register contains a value assigned to the TSB82AA2B device by TI. The device ID for the TSB82AA2B device is 8025h. Type: Offset: Default: Read only 02h 8025h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 1 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 3.4 Command Register The command register provides control over the TSB82AA2B interface to the PCI bus.
3.5 Status Register The status register provides status over the TSB82AA2B interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification. See Table 3−4 for a complete description of the register contents. Type: Offset: Default: Read/Clear/Update, Read only 06h 0210h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 Table 3−4.
3.6 Class Code and Revision ID Register The class code and revision ID register categorizes the TSB82AA2B device as a serial bus controller (0Ch), controlling an IEEE Std 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See Table 3−5 for a complete description of the register contents.
3.8 Header Type and BIST Registers The header type and built-in self-test (BIST) registers indicate the TSB82AA2B PCI header type, and indicate no built-in self test. See Table 3−7 for a complete description of the register contents. Type: Offset: Default: Read only 0Eh 0000h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3−7.
3.10 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of memory address space are required for the TI registers. See Table 3−9 for a complete description of the register contents.
3.11 CardBus CIS Base Address Register The TSB82AA2B device may be configured to support CardBus registers via bit 6 (CARDBUS) in the PCI miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.23, Miscellaneous Configuration Register). If CARDBUS is low (default), this 32-bit register returns 0s when read. If CARDBUS is high, this register is to be programmed with a base address referencing the memory-mapped card information structure (CIS).
3.12 CardBus CIS Pointer Register The TSB82AA2B device may be configured to support CardBus registers via bit 6 (CARDBUS) in the PCI miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.23, Miscellaneous Configuration Register). If CARDBUS is low (default), this register is read-only returning 0s when read. If CARDBUS is high, this register contains the pointer to the CardBus card information structure (CIS).
3.13 Subsystem ID Registers The subsystem ID registers are used for system and option card identification purposes. These registers can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 3.25, Subsystem Access Register). See Table 3−12 for a complete description of register contents.
3.15 Interrupt Line and Interrupt Pin Registers The interrupt line and interrupt pin registers communicate interrupt line routing information. See Table 3−13 for a complete description of the register contents. Type: Offset: Default: Read/Write, Read only 3Ch 0100h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Table 3−13.
3.17 OHCI Control Register The OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support. See Table 3−15 for a complete description of the register contents.
3.19 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the TSB82AA2B device related to PCI power management. See Table 3−17 for a complete description of the register contents. Type: Offset: Default: Read/Update, Read only 46h 7E02h Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 Table 3−17.
3.20 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power management function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 3−18 for a complete description of the register contents.
3.22 Multifunction Select Register The multifunction select register provides a method. See Table 3−20 for a complete description of the register contents. Type: Offset: Default: Bit 31 Read/Write/Update, Read only E8h 0000 0000h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 3−20.
3.23 Miscellaneous Configuration Register The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3−21 for a complete description of the register contents.
3.24 Link Enhancement Control Register The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1. See Table 3−22 for a complete description of the register contents.
Table 3−22. Link Enhancement Control Register Description (Continued) BIT FIELD NAME TYPE 5−3 RSVD R DESCRIPTION 2 enab_insert_idle R/W Enable insert idle (OHCI-Lynx compatible). When the PHY device has control of the PHY_CTL0−PHY_CTL1 control lines and PHY_DATA0−PHY_DATA7 data lines and the link requests control, the PHY device drives 11b on the PHY_CTL0−PHY_CTL1 lines. The link can then start driving these lines immediately.
3.26 GPIO Control Register The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See Table 3−24 for a complete description of the register contents.
4 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory mapped into a 2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 3.9, OHCI Base Address Register). These registers are the primary interface for controlling the TSB82AA2B IEEE Std 1394 link function. This section provides the register interface and bit descriptions.
Table 4−1.
Table 4−1.
4.1 OHCI Version Register The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. See Table 4−2 for a complete description of the register contents. Type: Offset: Default: Bit 31 Read only 00h 0X01 0010h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Default 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 1 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 Table 4−2.
4.3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the TSB82AA2B device attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 4−4 for a complete description of the register contents.
4.6 CSR Control Register The CSR control register accesses the bus management CSR registers from the host through compare-swap operations. This register controls the compare-swap operation and selects the CSR resource. See Table 4−5 for a complete description of the register contents.
4.8 Bus ID Register The bus ID register externally maps to the first quadlet in the Bus_Info_Block and contains the constant 3133 3934h, which is the ASCII value of 1394.
4.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 4−7 for a complete description of the register contents. Type: Offset: Default: Bit 31 Read/Write, Read only 20h X0XX B0X2h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Default X X X X 0 0 0 0 X X X X X X X X Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 1 0 1 1 0 0 0 0 X X 0 0 0 0 1 0 Table 4−7.
4.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID), which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a system (hardware) reset, which is an illegal GUID value. If a serial EEPROM is detected, the contents of this register are loaded through the serial EEPROM interface after a G_RST. At that point, the contents of this register cannot be changed.
4.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See Table 4−8 for a complete description of the register contents.
4.15 Vendor ID Register The vendor ID register provides the company ID of an organization that specifies any vendor-unique registers or features. The TSB82AA2B device implements several unique features with regards to OHCI. Therefore, bits 23−0 are programmed with TI OUI, 0X08 0028.
4.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the TSB82AA2B device. See Table 4−12 for a complete description of the register contents.
Table 4−12. Host Controller Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 19 LPS RSC Bit 19 controls the link power status. Software must set this bit to 1 to permit link-PHY communication. A 0 prevents link-PHY communication. The OHCI-link is divided into two clock domains (PCI_CLK and PHY_SCLK). If software tries to access any register in the PHY_SCLK domain while the PHY_SCLK is disabled, a target abort is issued by the link.
4.18 Self-ID Count Register The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 4−13 for a complete description of the register contents.
4.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register enables packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register. See Table 4−14 for a complete description of the register contents.
4.20 Isochronous Receive Channel Mask Low Register The isochronous receive channel mask low set/clear register enables packet receives from the lower 32 isochronous data channels. See Table 4−15 for a complete description of the register contents.
4.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various TSB82AA2B interrupt sources. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register.
Table 4−16. Interrupt Event Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 22 cycleLost RSCU A lost cycle is indicated when no cycle_start packet is sent or received between two successive cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after a cycleSynch event without an intervening cycle start.
4.22 Interrupt Mask Register The interrupt mask set/clear register enables the various TSB82AA2B interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register. In all cases, except bit 31 (masterIntEnable) and bit 30 (VendorSpecific), the enables for each interrupt event align with the interrupt event register bits detailed in Table 4−16.
Table 4−17. Interrupt Mask Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 20 cycleSynch RSC When this bit and bit 20 (cycleSynch) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this isochronous-cycle interrupt mask enables interrupt generation. 19 phy RSC When this bit and bit 19 (phy) in the interrupt event register at OHCI offset 80h/84h (see Section 4.
4.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set to 1. Upon determining that the isochTx (bit 6) interrupt has occurred in the interrupt event register at OHCI offset 80h/84h (see Section 4.
4.25 Isochronous Receive Interrupt Event Register The isochronous receive interrupt event set/clear register reflects the interrupt state of the isochronous receive contexts. An interrupt is generated on behalf of an isochronous receive context if an INPUT_* command completes and its interrupt bits are set to 1. Upon determining that the isochRx (bit 7) interrupt in the interrupt event register at OHCI offset 80h/84h (see Section 4.
4.27 Initial Bandwidth Available Register The initial bandwidth available register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 4−20 for a complete description of the register contents.
4.29 Initial Channels Available Low Register The initial channels available low register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 4−22 for a complete description of the register contents.
4.31 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the TSB82AA2B device. It contains controls for the receiver and cycle timer. See Table 4−24 for a complete description of the register contents.
4.32 Node ID Register The node ID register contains the address of the node on which the OHCI-Lynx chip resides, and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15−6) and the NodeNumber field (bits 5−0) is referred to as the node ID. See Table 4−25 for a complete description of the register contents.
4.33 PHY Control Register The PHY control register reads from or writes to a PHY register. See Table 4−26 for a complete description of the register contents. Type: Offset: Default: Bit 31 Read/Write/Update, Read/Write, Read/Update, Read only ECh 0000 0000h 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Table 4−26.
4.35 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set to 1 in this register, then the packet is not acknowledged and the request is not queued.
Table 4−28. Asynchronous Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 16 asynReqResource48 RSC If bit 16 is set to 1 for local bus node number 48, asynchronous requests received by the TSB82AA2B device from that node are accepted. 15 asynReqResource47 RSC If bit 15 is set to 1 for local bus node number 47, asynchronous requests received by the TSB82AA2B device from that node are accepted.
4.36 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register. None of the bits in this register can be accessed while a bus reset interrupt is pending in the interrupt event register at 80h/84h.
4.37 Physical Request Filter High Register The physical request filter high set/clear register enables physical receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for the physical request context and the node ID has been compared against the ARRQ registers, the comparison is done again with this register. If the bit corresponding to the node ID is not set to 1 in this register, the request is handled by the ARRQ context instead of the physical request context.
Table 4−30. Physical Request Filter High Register Description (Continued) 4−32 BIT FIELD NAME TYPE DESCRIPTION 16 physReqResource48 RSC If bit 16 is set to 1 for local bus node number 48, physical requests received by the TSB82AA2B device from that node are handled through the physical request context. 15 physReqResource47 RSC If bit 15 is set to 1 for local bus node number 47, physical requests received by the TSB82AA2B device from that node are handled through the physical request context.
4.38 Physical Request Filter Low Register The physical request filter low set/clear register enables physical receive requests on a per-node basis, and handles the lower node IDs. When a packet is destined for the physical request context and the node ID has been compared against the asynchronous request filter registers, the node ID comparison is done again with this register.
4.40 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See Table 4−32 for a complete description of the register contents.
4.41 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the TSB82AA2B device accesses when software enables the context by setting bit 15 (run) of the asynchronous context control register (see Section 4.40, Asynchronous Context Control Register) to 1. See Table 4−33 for a complete description of the register contents.
4.42 Isochronous Transmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …, 7). See Table 4−34 for a complete description of the register contents.
4.43 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the TSB82AA2B device accesses when software enables an isochronous transmit context by setting bit 15 (run) in the isochronous transmit context control register (see Section 4.42, Isochronous Transmit Context Control Register) to 1. The isochronous transmit DMA context command pointer can be read when a context is active.
Table 4−35. Isochronous Receive Context Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 28 multiChanMode RSC When bit 28 is set to 1, the corresponding isochronous receive DMA context receives packets for all isochronous channels enabled in the isochronous receive channel mask high register at OHCI offset 70h/74h (see Section 4.19, Isochronous Receive Channel Mask High) and isochronous receive channel mask low register at OHCI offset 78h/7Ch (see Section 4.
4.45 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the TSB82AA2B device accesses when software enables an isochronous receive context by setting bit 15 (run) in the isochronous receive context control register (see Section 4.44, Isochronous Receive Context Control Register) to 1. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).
4.46 Isochronous Receive Context Match Register The isochronous receive context match register starts an isochronous receive context running on a specified cycle number, filters incoming isochronous packets based on tag values, and waits for packets with a specified sync value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 4−36 for a complete description of the register contents.
5 TI Extension Registers The TI extension base address register provides a method of accessing memory-mapped TI extension registers. The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. See Section 3.10, TI Extension Base Address Register, for register bit field details. See Table 5−1 for the TI extension register listing. Table 5−1.
5.3 Isochronous Receive DV Enhancements The DV frame sync and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394 DV data that is received in the correct order to DV frame-sized data buffers described by several INPUT_MORE descriptors (see 1394 Open Host Controller Interface Specification, Revision 1.1).
Table 5−2. Isochronous Receive Digital Video Enhancements Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 4 CIP_Strip1 RSC When bit 4 is set to 1, the isochronous receive context 1 strips the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 420h/424h (see Section 4.44, Isochronous Receive Context Control Register) is 0.
5.5 Link Enhancement Control Register This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM, if one is present, as noted in the bit descriptions below.
Table 5−3. Link Enhancement Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 6 RSVD R This bit is not assigned in the TSB82AA2B follow-on products, since this bit location loaded by the serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register). Reserved. Bits 5−3 return 0s when read.
5.6 Isochronous Transmit Context n Timestamp Offset Registers The value of these registers is added as an offset to the cycle timer value when using the MPEG, DV, and CIP enhancements. A timestamp offset register is implemented per isochronous transmit context. The n value following the offset indicates the context number (n = 0, 1, 2, 3, …, 7). These registers are programmed by software as appropriate. See Table 5−4 for a complete description of the register contents.
6 General-Purpose Input/Output (GPIO) Interface The GPIO interface consists of one GPIO port available via the MFUNC terminal by configuring the multifunction configuration register (PCI offset E8h). GPIO powers up as a general-purpose input and is programmable via the GPIO control register. Figure 6−1 shows the logic diagram for GPIO implementation. GPIO Read Data GPIO Port GPIO Write Data D Q GPIO_Invert GPIO Enable Figure 6−1.
6−2
7 Serial EEPROM Interface The TSB82AA2B device provides a serial bus interface to initialize the 1394 global unique ID register and a few PCI configuration registers through a serial EEPROM. The TSB82AA2B device communicates with the serial EEPROM via the 2-wire serial interface. After power up, the serial interface initializes the locations listed in Table 7−1. While the TSB82AA2B device accesses the serial EEPROM, all incoming PCI slave accesses are terminated with retry status.
Table 7−1. Serial EEPROM Map BYTE ADDRESS 00 BYTE DESCRIPTION PCI maximum latency (PCI offset 3Eh) PCI minimum grant (PCI offset 3Fh) 01 PCI subsystem vendor ID alias (lsbyte) (PCI offset F8h) 02 PCI subsystem vendor ID alias (msbyte) (PCI offset F9h) 03 PCI subsystem ID alias (lsbyte) (PCI offset FAh) 04 PCI subsystem ID alias (msbyte) (PCI offset FBh) 05 [7] Link_enhancement Control.enab_unfair (PCI offset F4h, bit 7) [6] HCControl.
8 Electrical Characteristics 8.1 Absolute Maximum Ratings Over Operating Temperature Ranges† Supply voltage range: VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V VCCP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 5.5 V Input voltage range for PCI, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.2 Recommended Operating Conditions VCC Core voltage Commercial VCCP PCI I/O clamping voltage Commercial VIH† High-level g input p voltage g PCI OPERATION MIN NOM MAX UNIT 3.3 V 3 3.3 3.6 V 3.3 V 3 3.3 3.6 5V 4.5 5 5.5 3.3 V 0.475VCCP VCCP 5V 2 VCCP 2 3.6 3.3 V 0 0.325VCCP 5V 0 0.
8.3 Electrical Characteristics Over Recommended Operating Conditions (unless otherwise noted) TEST CONDITIONS OPERATION IOH = − 0.5 mA PCI VOH High level output voltage High-level PHY interface IOZ † Low level output voltage Low-level 3-state output high impedance IIL Low level input current Low-level IIH High level input current High-level MAX UNIT 0.9VCC IOH = − 2 mA 2.4 IOH = − 4 mA 2.8 IOH = − 8 mA VCC − 0.6 IOL = 1.5 mA PCI VOL† MIN V 0.1VCC IOL = 6 mA 0.
8−4
9 Mechanical Information The TSB82AA2B is packaged in a 144-terminal PGE and a 176-ball ZGW package. The following shows the mechanical dimensions for the PGE and ZGW packages. PGE (S-PQFP-G144) Plastic Quad Flatpack 108 73 109 72 0,27 0,17 0,08 M 0,50 144 0,13 NOM 37 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 0,25 0,05 MIN 0°− 7° 0,75 0,45 1,45 1,35 Seating Plane 1,60 MAX 0,08 4040147 / C 10/96 NOTES: A. All linear dimensions are in millimeters. B.
PACKAGE OPTION ADDENDUM www.ti.
MECHANICAL DATA MTQF017A – OCTOBER 1994 – REVISED DECEMBER 1996 PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 108 73 109 72 0,27 0,17 0,08 M 0,50 144 0,13 NOM 37 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040147 / C 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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