Datasheet

Each cell represents one clock sample period, and n is the number of bits in the request stream.
LR1
LR2 LR3 LR (n-2)LR0 LR (n-1)
TSB81BA3E
SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com
Figure 23. PINT (PHY Interrupt) Stream
Table 33. PHY Status Transfer Encoding
PI[1:3] NAME DESCRIPTION NUMBER OF BITS
000 NOP No status indication 5
Interrupt indication: configuration time-out, cable-power failure,
001 PHY_INTERRUPT 5
port event interrupt, or arbitration state machine time-out.
010 PHY_REGISTER_SOL Solicited PHY register read 17
011 PHY_REGISTER_UNSOL Unsolicited PHY register read 17
100 PH_RESTORE_NO_RESET PHY-link interface initialized; no bus resets occurred. 5
101 PH_RESTORE_RESET PHY-link interface initialized; a bus reset occurred. 5
110 INTERFACE_ERROR PHY received illegal request. 5
111 Reserved Reserved Reserved
Most PHY status transfers are 5 bits long. The transfer consists of a start bit (always 1), followed by a request
type (see Table 33), and lastly followed by a stop bit (always 0). The only exception is when the transfer of a
register contents occurs. Solicited and unsolicited PHY register read transfers are 17 bits long and include the
additional information of the register address and the data contents of the register (see Table 34).
Table 34. Register Read (Solicited and Unsolicited) PHY Status Transfer Encoding
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1–3 Request type A 010 or a 011 indicates a solicited or unsolicited register contents transfer.
4–7 Address Identifies the address of the PHY register whose contents are being transferred
8–15 Data The contents of the register specified in bits 4 through 7
16 Stop bit Indicates the end of the transfer (always 0)
Receive
When the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting receive
on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The PHY indicates the start of
a packet by placing the speed code (encoded as shown in Table 35) on the D terminals, followed by packet data.
The PHY holds the CTL terminals in the receive state until the last symbol of the packet has been transferred.
The PHY indicates the end of packet data by asserting idle on the CTL terminals. All received packets are
transferred to the LLC. Note that the speed code is part of the PHY-LLC protocol and is not included in the
calculation of CRC or any other data protection mechanisms.
The PHY can optionally send status information to the LLC at anytime during the data-on indication. Only bus
status transfer information can be sent during a data-on indication. The PHY holds the CTL terminals in the
status state for 1 PCLK cycle and modifies the D terminals to the correct status state. Note that the status
transfer during the data-on indication does not need to be preceded or followed by a data-on indication.
It is possible for the PHY to receive a null packet, which consists of the data-prefix state on the serial bus
followed by the data-end state, without any packet data. A null packet is transmitted whenever the packet speed
exceeds the capability of the receiving PHY, or whenever the LLC immediately releases the bus without
transmitting any data. In this case, the PHY asserts receive on the CTL terminals with the data-on indication (all
1s) on the D terminals, followed by idle on the CTL terminals, without any speed code or data being transferred.
In all cases, in normal operation, the TSB81BA3E sends at least one data-on indication before sending the
speed code or terminating the receive operation.
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