Datasheet

D[0:7]

ST XX

CTL[0:1]

01 XX

Status Bits

TSB81BA3E

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SLLS783A –MAY 2009–REVISED MAY 2010

Status Transfer

A status transfer is initiated by the PHY when status information is to be transferred to the LLC. Two types of

status transfers can occur: bus status transfer and PHY status transfer. Bus status transfers send the following

status information: bus reset indications, subaction and arbitration reset gap indications, cycle start indications,

and PHY interface reset indications. PHY status transfers send the following information: PHY interrupt

indications, unsolicited and solicited PHY register data, bus initialization indications, and PHY-link interface error

indications. The PHY uses a different mechanism to send the bus status transfer and the PHY status transfer.

Bus status transfers use the CTL0-CTL1 and D0-D7 terminals to transfer status information. Bus status transfers

can occur during idle periods on the PHY-link interface or during packet reception. When the status transfer

occurs, a single PCLK cycle of status information is sent to the LLC. The information is sent such that each

individual Dn terminal conveys a different bus status transfer event. During any bus status transfer, only one

status bit is set. If the PHY-link interface is inactive, then the status information is not sent. When a bus reset on

the serial bus occurs, the PHY sends a bus reset indication (via the CTLn and Dn terminals), cancels all packet

transfer requests, sets asynchronous and isochronous phases to even, forwards self-ID packets to the link, and

sends an unsolicited PHY register 0 status transfer (via the PINT terminal) to the LLC. In the case of a PHY

interface reset operation, the PHY-link interface is reset on the following PCLK cycle.

Table 32 shows the definition of the bits during the bus status transfer and Figure 22 shows the timing.

Table 32. Status Bits

STATUS BIT DESCRIPTION

D0 Bus reset

D1 Arbitration reset gap – odd

D2 Arbitration reset gap – even

D3 Cycle start – odd

D4 Cycle start – even

D5 Subaction gap

D6 PHY interface reset

D7 Reserved

Figure 22. Bus Status Transfer Timing

PHY status transfers use the PINT terminal to send status information serially to the LLC as shown in Figure 23.

PHY status transfers (see Table 33) can occur at any time during normal operation. The PHY uses the

PHY_INTERRUPT PHY status transfer when required to interrupt the LLC due to a configuration time-out, a

cable-power failure, a port interrupt, or an arbitration time-out. When transferring PHY register contents, the PHY

uses either the solicited or the unsolicited register read status transfer. The unsolicited register 0 contents are

passed to the LLC only during initialization of the serial bus. After any PHY-link interface initialization, the PHY

sends a PHY status transfer indicating whether or not a bus reset occurred during the inactive period of the

PHY-link interface. If the PHY receives an illegal request from the LLC, then the PHY issues an

INTERFACE_ERROR PHY status transfer.

Product Folder Link(s): TSB81BA3E