Datasheet

TSB81BA3E
SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com
NOTE
The TSB81BA3E accepts a bus request with an invalid speed code and processes the
bus request normally. However, during packet transmission for such a request, the
TSB81BA3E ignores any data presented by the LLC and transmits a null packet.
For a read register request, the length of the LREQ bit stream is 10 bits as shown in Table 29.
Table 29. Read Register Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1–4 Request type A 1010 indicates this is a read register request.
5–8 Address Identifies the address of the PHY register to be read
9 Stop bit Indicates the end of the transfer (always 0)
For a write register request, the length of the LREQ bit stream is 18 bits as shown in Table 30.
Table 30. Write Register Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1–4 Request type A 1010 indicates this is a write register request.
5–8 Address Identifies the address of the PHY register to be writer
9–16 Data Gives the data that is to be written to the specified register address
17 Stop bit Indicates the end of the transfer (always 0)
For a link notification request, the length of the LREQ bit stream is 6 bits as shown in Table 31.
Table 31. Link Notification Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1–4 Request type A 1100, 1101, or 1110 indicates this is a link notification request.
5 Stop bit Indicates the end of the transfer (always 0)
For fair or priority access, the LLC sends a bus request at least one clock after the PHY-LLC interface becomes
idle. The PHY queues all bus requests and can queue one request of each type. If the LLC issues a different
request of the same type, then the new request overwrites any nonserviced request of that type. On the receipt
(CTL terminals are asserted to the receive state, 10b) of a packet, queued requests are not cleared by the PHY.
The cycle master node uses a cycle start request (Cyc_Start_Req) to send a cycle start message. After receiving
or transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears
an isochronous request only when the serial bus has been won.
To send an acknowledge packet, the LLC must issue an immediate bus request (Immed_Req) during the
reception of the packet addressed to it. This is required to minimize the idle gap between the end of the received
packet and the start of the transmitted acknowledge packet. As soon as the received packet ends, the PHY
immediately grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the
header CRC of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but
instead cancels the transmit operation and releases the interface immediately; the LLC must not use this grant to
send another type of packet. After the interface is released the LLC can proceed with another request.
For write register requests, the PHY loads the specified data into the addressed register as soon as the request
transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the
LLC at the next opportunity through a PHY status transfer. A write or read register request can be made at any
time, including while a bus request is pending. Once a read register request is made, the PHY ignores further
read register requests until the register contents are successfully transferred to the LLC. A bus reset does not
clear a pending read register request.
44 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TSB81BA3E