Datasheet

Each cell represents one clock sample period, and n is the number of bits in the request stream.
LR1
LR2 LR3 LR (n-2)LR0 LR (n-1)
TSB81BA3E
SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com
Table 22. CTL Encoding When PHY Has Control of the Bus
CTL0 CTL1 NAME DESCRIPTION
0 0 Idle No activity (this is the default mode)
0 1 Status Status information is being sent from the PHY to the LLC.
1 0 Receive An incoming packet is being sent from the PHY to the LLC.
1 1 Grant The LLC has been given control of the bus to send an outgoing packet.
Table 23. CTL Encoding When LLC Has Control of the Bus
CTL0 CTL1 NAME DESCRIPTION
0 0 Idle The LLC releases the bus (transmission has been completed).
0 1 Transmit An outgoing packet is being sent from the LLC to the PHY.
1 0 Reserved Reserved
The LLC is holding the bus while data is being prepared for transmission, or the LLC is sending a
1 1 Holation request to arbitrate for access to the bus, or the LLC is identifying the end of a subaction gap to
the PHY.
LLC Service Request
To request access to the bus, to read or write a PHY register, or to send a link notification to PHY, the LLC
sends a serial bit stream on the LREQ terminal as shown in Figure 21.
Figure 21. LREQ Request Stream
The length of the stream varies depending on the type of request as shown in Table 24.
Table 24. Request Stream Bit Length
REQUEST TYPE NUMBER OF BITS
Bus request 11
Read register request 10
Write register request 18
Link notification request 6
PHY-link interface reset request 6
Regardless of the type of request, a start bit of 1 is required at the beginning of the stream and a stop bit of 0 is
required at the end of the stream. The second through fifth bits of the request stream indicate the type of the
request. In the descriptions in Table 25, bit LR1 is the most significant and is transmitted first in the request bit
stream. The LREQ terminal is normally low.
Table 25 shows the encoding for the request type.
Table 25. Request Type Encoding
LR1-LR4 NAME DESCRIPTION
0000 Reserved Reserved
0001 Immed_Req Immediate request. On detection of idle, the PHY arbitrates for the bus.
Next even request. The PHY arbitrates for the bus to send an asynchronous packet in the even
0010 Next_Even
fairness interval phase.
Next odd request. The PHY arbitrates for the bus to send an asynchronous packet in the odd fairness
0011 Next_Odd
interval phase.
42 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TSB81BA3E