Datasheet

S5_LKON
LPS
PCLK
LREQ
D0–D7
CTL0–CTL1
Link-Layer
Controller
TSB41BA3B
LCLK_PMC
PINT
TSB81BA3E
www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010
Figure 20. PHY-LLC Interface
The LCLK terminal provides a clock signal to the PHY. The LLC derives this clock from the PCLK signal and is
phase-locked to the PCLK signal. All LLC to PHY transfers are synchronous to LCLK.
The PCLK terminal provides a 98.304-MHz interface system clock. All control, data, and PHY interrupt signals
are synchronized to the rising edge of PCLK.
The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data
between the TSB81BA3E and LLC.
The D0−D7 terminals form a bidirectional data bus, which transfers status information, control information, or
packet data between the devices. The TSB81BA3E supports S400B and S800 data transfers over the D0−D7
data bus. In S400B and S800 operation all Dn terminals are used.
The LREQ terminal is controlled by the LLC to send serial service requests to the PHY to request access to the
serial-bus for packet transmission, read or write PHY registers, or control arbitration acceleration. All data on
LREQ is synchronous to LCLK.
The LPS and LKON/DS2 terminals are used for power management of the PHY and LLC. The LPS terminal
indicates the power status of the LLC, and may be used to reset the PHY-LLC interface or to disable PCLK. The
LKON/DS2 terminal sends a wake-up notification to the LLC and indicates an interrupt to the LLC when either
LPS is inactive or the PHY register L bit is 0.
The PINT terminal is used by the PHY for the serial transfer of status, interrupt, and other information to the LLC.
The TSB81BA3E normally controls the CTL0-CTL1 and D0-D7 bidirectional buses. The LLC is allowed to drive
these buses only after the LLC has been granted permission to do so by the PHY.
There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data
transmit, and data receive. The LLC issues a service request to read or write a PHY register or to request the
PHY to gain control of the serial-bus in order to transmit a packet.
The PHY may initiate a status transfer either autonomously or in response to a register read request from the
LLC.
The PHY initiates a receive operation when a packet is received from the serial-bus.
The PHY initiates a transmit operation after winning control of the serial-bus following a bus-request by the LLC.
The transmit operation is initiated when the PHY grants control of the interface to the LLC.
Table 22 and Table 23 show the encoding of the CTL0-CTL1 bus.
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