Datasheet

PCLK
(a) (c)
(b)
CTL0, CTL1
D0–D7
LREQ
LPS
(d)
t
LPS_RESET
t
RESTORE
TSB81BA3E
SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com
Table 21. LPS Timing Parameters (continued)
SYMBOL DESCRIPTION MIN MAX UNIT
t
LPS_DISABLE
Time for PHY to recognize LPS deasserted and disable the interface 26.03 26.11 ms
t
RESTORE
Time to permit optional isolation circuits to restore during an interface reset 15 23
(3)
ms
PHY not in low-power state 60 ns
t
CLK_ACTIVATE
Time for PCLK to be activated from reassertion of LPS
PHY in low-power state 5.3 7.3 ms
(3) The maximum value for t
RESTORE
does not apply when the PHY-LLC interface is disabled, in which case an indefinite time can elapse
before LPS is reasserted. Otherwise, in order to reset but not disable the interface, it is necessary that the LLC ensure that LPS is
deasserted for less than t
LPS_DISABLE
.
The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and request
activity. When the PHY observes that LPS has been deasserted for t
LPS_RESET
, it resets the interface. When the
interface is in the reset state, the PHY sets its CTL and D outputs in the logic 0 state and ignores any activity on
the LREQ signal. Figure 17 shows the timing for interface reset.
Figure 17. Interface Reset
The sequence of events for resetting the PHY-LLC interface is as follows:
a. Normal operation. Interface is operating normally, with LPS asserted, PCLK active, status and packet data
reception and transmission via the CTL and D lines, and request activity via the LREQ line. In Figure 17, the
LPS signal is shown as a nonpulsed level signal. However, it is permissible to use a pulsed signal for LPS in
a direct connection between the PHY and LLC; a pulsed signal is required when using an isolation barrier.
b. LPS deasserted. The LLC deasserts the LPS signal and, within 1 ms, terminates any request or interface bus
activity, places its CTL and D outputs into the high-impedance state, and drives its LREQ output low.
c. Interface reset. After t
LPS_RESET
time, the PHY determines that LPS is inactive, terminates any interface bus
activity, and drives its CTL and D outputs low. The PHY-LLC interface is now in the reset state.
d. Interface restored. After the minimum t
RESTORE
time, the LLC can again assert LPS active. When LPS is
asserted, the interface is initialized as described in the following paragraph.
If the LLC continues to keep the LPS signal deasserted, it then requests that the interface be disabled. The PHY
disables the interface when it observes that LPS has been deasserted for t
LPS_DISABLE
. When the interface is
disabled, the PHY sets its CTL and D outputs as previously stated for interface reset, but also stops PCLK
activity. The interface is also placed into the disabled condition on a hardware reset of the PHY. Figure 18 shows
the timing for the interface disable.
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