Datasheet

00
00 0000
(e)(d)(c)(b)(a)
01
00
000011
D0–D7
CTL0, CTL1
SYSCLK
00
Link Controls CTL and D
PHY High-Impedance CTL and D Outputs
TSB81BA3E
www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010
Figure 16. Cancelled/Null Packet Transmission
The sequence of events for a cancelled/null packet transmission is as follows:
a. Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the
interface to the link.
b. Optional idle cycle. The link can assert at most one idle cycle preceding assertion of hold. This idle cycle is
optional; the link is not required to assert idle preceding hold.
c. Optional hold cycles. The link can assert hold for up to 47 cycles preceding assertion of idle. These hold
cycle(s) are optional; the link is not required to assert hold preceding idle.
d. Null transmit termination. The null transmit operation is terminated by the link asserting two cycles of idle on
the CTL lines and then releasing the interface and returning control to the PHY. Note that the link can assert
idle for a total of three consecutive cycles if it asserts the optional first idle cycle but does not assert hold. It
is recommended that the link assert three cycles of idle to cancel a packet transmission if no hold cycles are
asserted. This ensures that either the link or PHY controls the interface in all cycles.
e. After regaining control of the interface, the PHY asserts at least one idle cycle before any subsequent status
transfer, receive operation, or transmit operation.
Interface Reset and Disable
The LLC controls the state of the PHY-LLC interface using the LPS signal. The interface can be placed into a
reset state, a disabled state, or be made to initialize and then return to normal operation. When the interface is
not operational (whether reset, disabled, or in the process of initialization), the PHY cancels any outstanding bus
request or register read request, and ignores any requests made via the LREQ line. Additionally, any status
information generated by the PHY is not queued and does not cause a status transfer on restoration of the
interface to normal operation.
The LPS signal can be either a level signal or a pulsed signal, depending on whether the PHY-LLC interface is a
direct connection or is made across an isolation barrier. When an isolation barrier exists between the PHY and
LLC, the LPS signal must be pulsed. In a direct connection, the LPS signal can be either a pulsed or a level
signal. Timing parameters for the LPS signal are given in Table 21.
Table 21. LPS Timing Parameters
SYMBOL DESCRIPTION MIN MAX UNIT
t
LPSL
LPS low time (when pulsed)
(1)
0.09 2.6 ms
t
LPSH
LPS high time (when pulsed)
(1)
0.021 2.6 ms
t
LPS_DUTY
PS duty cycle (when pulsed)
(2)
20% 60%
t
LPS_RESET
Time for PHY to recognize LPS deasserted and reset the interface 2.6 2.68 ms
(1) The specified t
LPSL
and t
LPSH
times are worst-case values appropriate for operation with the TSB81BA3E. These values are broader
than those specified for the same parameters in the 1394a-2000 Supplement (that is, an implementation of LPS that meets the
requirements of 1394a-2000 operates correctly with the TSB81BA3E).
(2) A pulsed LPS signal must have a duty cycle (ratio of t
LPSH
to cycle period) in the specified range to ensure proper operation when using
an isolation barrier on the LPS signal (for example, as shown in Figure 8).
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 37
Product Folder Link(s): TSB81BA3E