Datasheet

00 000010

(g)(e)/(f)(d)(c)(b)(a)

000000

000011

dnd0, d1, . . .

Link Controls CTL and D

PHY High-Impedance CTL and D Outputs

D0–D7

CTL0, CTL1

SYSCLK

NOTE A: SPD = Speed code, see NO TAG. d0–dn = Packet data

00/01

00/SP

TSB81BA3E

SLLS783A –MAY 2009–REVISED MAY 2010

www.ti.com

A. SPD = Speed code, see Table 20 d0-dn = Packet data

Figure 15. Normal Packet Transmission Timing

The sequence of events for a normal packet transmission is as follows:

a. Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over control of

the interface to the link so that the link can transmit a packet. The PHY releases control of the interface (that

is, it places its CTL and D outputs in a high-impedance state) following the idle cycle.

b. Optional idle cycle. The link can assert at most one idle cycle preceding assertion of either hold or transmit.

This idle cycle is optional; the link is not required to assert idle preceding either hold or transmit.

c. Optional hold cycles. The link can assert hold for up to 47 cycles preceding assertion of transmit. These hold

cycle(s) are optional; the link is not required to assert hold preceding transmit.

d. Transmit data. When data is ready to be transmitted, the link asserts transmit on the CTL lines along with the

data on the D lines.

e. Transmit operation terminated. The transmit operation is terminated by the link asserting hold or idle on the

CTL lines. The link asserts hold to indicate that the PHY is to retain control of the serial bus in order to

transmit a concatenated packet. The link asserts idle to indicate that packet transmission is complete and the

PHY can release the serial bus. The link then asserts idle for one more cycle following this hold or idle cycle

before releasing the interface and returning control to the PHY.

f. Concatenated packet speed code. If multispeed concatenation is enabled in the PHY, then the link asserts a

speed code on the D lines when it asserts hold to terminate packet transmission. This speed code indicates

the transmission speed for the concatenated packet that is to follow. The encoding for this concatenated

packet speed code is the same as the encoding for the received packet speed code (see Table 20). The link

cannot concatenate an S100 packet onto any higher-speed packet.

g. After regaining control of the interface, the PHY asserts at least one idle cycle before any subsequent status

transfer, receive operation, or transmit operation.

Product Folder Link(s): TSB81BA3E