Datasheet

TSB81BA3E

www.ti.com

SLLS783A –MAY 2009–REVISED MAY 2010

Table 20. Receive Speed Codes

D0-D7

(1)

DATA RATE

00XX XXXX S100

0100 XXXX S200

0101 0000 S400

11YY YYYY data-on indication

(1) X = Output as 0 by PHY, ignored by LLC.

Y = Output as 1 by PHY, ignored by LLC.

Transmit

When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If

the PHY wins arbitration for the serial bus, then the PHY-LLC interface bus is granted to the LLC by asserting

the grant state (11b) on the CTL terminals for one PCLK cycle, followed by idle for one clock cycle. The LLC then

takes control of the bus by asserting either idle (00b), hold (01b) or transmit (10b) on the CTL terminals. Unless

the LLC is immediately releasing the interface, the LLC can assert the idle state for at most one clock before it

must assert either hold or transmit on the CTL terminals. The hold state is used by the LLC to retain control of

the bus while it prepares data for transmission. The LLC can assert hold for zero or more clock cycles (that is,

the LLC need not assert hold before transmit). The PHY asserts data-prefix on the serial bus during this time.

When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first

bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have

been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle and then asserts

idle for one additional cycle before releasing the interface bus and putting the CTL and D terminals in a

high-impedance state. The PHY then regains control of the interface bus.

The hold state asserted at the end-of-packet transmission indicates to the PHY that the LLC requests to send

another packet (concatenated packet) without releasing the serial bus. The PHY responds to this concatenation

request by waiting the required minimum packet separation time and then asserting grant as before. This

function can be used to send a unified response after sending an acknowledge or to send consecutive

isochronous packets during a single isochronous period. Unless multispeed concatenation is enabled, all packets

transmitted during a single bus ownership must be of the same speed (because the speed of the packet is set

before the first packet). If multispeed concatenation is enabled (when the EMSC bit of PHY register 5 is set),

then the LLC must specify the speed code of the next concatenated packet on the D terminals when it asserts

hold on the CTL terminals at the end of a packet. The encoding for this speed code is the same as the speed

code that precedes received packet data as given in Table 20.

After sending the last packet for the current bus ownership, the LLC releases the bus by asserting idle on the

CTL terminals for two clock cycles. The PHY begins asserting idle on the CTL terminals one clock after sampling

idle from the link. Note that whenever the D and CTL terminals change direction between the PHY and the LLC,

an extra clock period is allowed so that both sides of the interface can operate on registered versions of the

interface signals.

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