Datasheet

00
0010
XX dnd0SPD
(a) (b)
FF (data-on)
D0–D7
CTL0, CTL1
SYSCLK
(c) (d)
(e)
NOTE A: SPD = Speed code, see NO TAG. d0–dn = Packet data
00
0010
XX
(a)
(b) (c)
FF (data-on)D0–D7
CTL0, CTL1
SYSCLK
TSB81BA3E
SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com
A. SPD = Speed code, see Table 20 d0-dn = Packet data
Figure 13. Normal Packet Reception Timing
The sequence of events for a normal packet reception is as follows:
a. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.
Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a status
transfer operation that is in progress so that the CTL lines can change from status to receive without an
intervening idle.
b. Data-on indication. The PHY can assert the data-on indication code on the D lines for one or more cycles
preceding the speed code.
c. Speed code. The PHY indicates the speed of the received packet by asserting a speed code on the D lines
for one cycle immediately preceding packet data. The link decodes the speed code on the first receive cycle
for which the D lines are not the data-on code. If the speed code is invalid or indicates a speed higher than
that which the link is capable of handling, then the link must ignore the subsequent data.
d. Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data on
the D lines with receive on the CTL lines for the remainder of the receive operation.
e. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.
The PHY asserts at least one idle cycle following a receive operation.
Figure 14. Null Packet Reception Timing
The sequence of events for a null packet reception is as follows:
a. Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines.
Normally, the interface is idle when receive is asserted. However, the receive operation can interrupt a status
transfer operation that is in progress so that the CTL lines can change from status to receive without an
intervening idle.
b. Data-on indication. The PHY asserts the data-on indication code on the D lines for one or more cycles.
c. Receive operation terminated. The PHY terminates the receive operation by asserting idle on the CTL lines.
The PHY asserts at least one idle cycle following a receive operation.
34 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TSB81BA3E