Datasheet

TSB81BA3E
SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com
The TSB81BA3E includes several arbitration acceleration enhancements, which allow the PHY to improve bus
performance and throughput by reducing the number and length of interpacket gaps. These enhancements
include autonomous (fly-by) isochronous packet concatenation, autonomous fair and priority packet
concatenation onto acknowledge packets, and accelerated fair and priority request arbitration following
acknowledge packets. The enhancements are enabled when the EAA bit in PHY register 5 is set.
The arbitration acceleration enhancements can interfere with the ability of the cycle master node to transmit the
cycle start message under certain circumstances. The acceleration control request is therefore provided to allow
the LLC temporarily to enable or disable the arbitration acceleration enhancements of the TSB81BA3E during the
asynchronous period. The LLC typically disables the enhancements when its internal cycle counter rolls over,
indicating that a cycle-start message is imminent, and then re-enables the enhancements when it receives a
cycle-start message. The acceleration control request can be made at any time and is immediately serviced by
the PHY. Additionally, a bus reset or isochronous bus request causes the enhancements to be re-enabled, if the
EAA bit is set.
Status Transfer
A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY
waits until the interface is idle before starting the transfer. The transfer is initiated by the PHY asserting status
(01b) on the CTL terminals, along with the first two bits of status information on the D[0:1] terminals. The PHY
maintains CTL = Status for the duration of the status transfer. The PHY might prematurely end a status transfer
by asserting something other than status on the CTL terminals. This occurs if a packet is received before the
status transfer completes. The PHY continues to attempt to complete the transfer until all status information has
been successfully transmitted. At least one idle cycle occurs between consecutive status transfers.
The PHY normally sends just the first 4 bits of status to the LLC. These bits are status flags that are needed by
the LLC state machines. The PHY sends an entire 16-bit status packet to the LLC after a read register request,
or when the PHY has pertinent information to send to the LLC or transaction layers. The only defined condition
where the PHY automatically sends a register to the LLC is after self-ID, where the PHY sends the physical-ID
register that contains the new node address. All status transfers are either 4 or 16 bits unless interrupted by a
received packet. The status flags are considered to have been successfully transmitted to the LLC immediately
on being sent, even if a received packet subsequently interrupts the status transfer. Register contents are
considered to have been successfully transmitted only when all 8 bits of the register have been sent. A status
transfer is retried after being interrupted only if any status flags remain to be sent, or if a register transfer has not
yet completed.
Table 19 shows the definition of the bits in the status transfer, and Figure 12 shows the timing.
Table 19. Status Bits
BIT(s) NAME DESCRIPTION
Arbitration reset Indicates that the PHY has detected that the bus has been idle for an arbitration reset gap time (as
0
gap defined in the IEEE 1394a-2000 standard). This bit is used by the LLC in the busy/retry state machine.
Indicates that the PHY has detected that the bus has been idle for a subaction gap time (as defined in
1 Subaction gap the IEEE 1394a-2000 standard). This bit is used by the LLC to detect the completion of an isochronous
cycle.
2 Bus reset Indicates that the PHY has entered the bus reset state
Indicates that a PHY interrupt event has occurred. An interrupt event might be a configuration time-out,
3 Interrupt
a cable-power voltage falling too low, a state time-out, or a port status change.
4-7 Address This field holds the address of the PHY register whose contents are being transferred to the LLC.
8-15 Data This field holds the register contents.
32 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): TSB81BA3E