Datasheet

TSB81BA3E
www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010
Table 16. Read Register Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1-3 Request type A 100 indicates this is a read register request.
4-7 Address Identifies the address of the PHY register to be read
8 Stop bit Indicates the end of the transfer (always 0)
For a write register request, the length of the LREQ bit stream is 17 bits as shown in Table 17.
Table 17. Write Register Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1-3 Request type A 101 indicates this is a write register request.
4-7 Address Identifies the address of the PHY register to be written to
8-15 Data Gives the data that is to be written to the specified register address
16 Stop bit Indicates the end of the transfer (always 0)
For an acceleration control request, the length of the LREQ data stream is 6 bits as shown in Table 18.
Table 18. Acceleration Control Request
BIT(s) NAME DESCRIPTION
0 Start bit Indicates the beginning of the transfer (always 1)
1-3 Request type A 110 indicates this is an acceleration control request.
4 Control Asynchronous period arbitration acceleration is enabled if 1 and disabled if 0
5 Stop bit Indicates the end of the transfer (always 0)
For fair or priority access, the LLC sends the bus request (FairReq or PriReq) at least one clock after the
PHY-LLC interface becomes idle. If the CTL terminals are asserted to the receive state (10b) by the PHY, then
any pending fair or priority request is lost (cleared). Additionally, the PHY ignores any fair or priority requests if
the receive state is asserted while the LLC is sending the request. The LLC can then reissue the request one
clock after the next interface idle.
The cycle master node uses a priority bus request (PriReq) to send a cycle start message. After receiving or
transmitting a cycle start message, the LLC can issue an isochronous bus request (IsoReq). The PHY clears an
isochronous request only when the serial bus has been won.
To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception
of the packet addressed to it. This is required to minimize the idle gap between the end of the received packet
and the start of the transmitted acknowledge packet. As soon as the receive packet ends, the PHY immediately
grants control of the bus to the LLC. The LLC sends an acknowledgment to the sender unless the header CRC
of the received packet is corrupted. In this case, the LLC does not transmit an acknowledge, but instead cancels
the transmit operation and immediately releases the interface; the LLC must not use this grant to send another
type of packet. After the interface is released, the LLC can proceed with another request.
The LLC can make only one bus request at a time. Once the LLC issues any request for bus access (ImmReq,
IsoReq, FairReq, or PriReq), it cannot issue another bus request until the PHY indicates that the bus request
was lost (bus arbitration lost and another packet received), or won (bus arbitration won and the LLC granted
control). The PHY ignores new bus requests while a previous bus request is pending. All bus requests are
cleared on a bus reset.
For write register requests, the PHY loads the specified data into the addressed register as soon as the request
transfer is complete. For read register requests, the PHY returns the contents of the addressed register to the
LLC at the next opportunity through a status transfer. If a received packet interrupts the status transfer, then the
PHY continues to attempt the transfer of the requested register until it is successful. A write or read register
request can be made at any time, including while a bus request is pending. Once a read register request is
made, the PHY ignores further read register requests until the register contents are successfully transferred to
the LLC. A bus reset does not clear a pending read register request.
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