Datasheet

Each cell represents one clock sample period, and n is the number of bits in the request stream.
LR1
LR2 LR3 LR (n-2)LR0 LR (n-1)
TSB81BA3E
www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010
The D0-D7 terminals form a bidirectional data bus, which transfers status information, control information, or
packet data between the devices. The TSB81BA3E supports S100, S200, and S400 data transfers over the
D0-D7 data bus. In S100 operation, only the D0 and D1 terminals are used; in S200 operation, only the D0-D3
terminals are used; and in S400 operation, all D0-D7 terminals are used for data transfer. When the TSB81BA3E
is in control of the D0-D7 bus, unused Dn terminals are driven low during S100 and S200 operations. When the
LLC is in control of the D0-D7 bus, unused Dn terminals are ignored by the TSB81BA3E.
The LREQ terminal is controlled by the LLC to send serial service requests to the PHY to request access to the
serial bus for packet transmission, read or write PHY registers, or control arbitration acceleration.
The LPS and LKON/DS2 terminals are used for power management of the PHY and LLC. The LPS terminal
indicates the power status of the LLC and can be used to reset the PHY-LLC interface or to disable PCLK. The
LKON/DS2 terminal sends a wake-up notification to the LLC or external circuitry and indicates an interrupt to the
LLC when either LPS is inactive or the PHY register L bit is 0.
The TSB81BA3E normally controls the CTL0-CTL1 and D0-D7 bidirectional buses. The LLC is allowed to drive
these buses only after the LLC has been granted permission to do so by the PHY.
There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data
transmit, and data receive. The LLC issues a service request to read or write a PHY register, to request the PHY
to gain control of the serial-bus in order to transmit a packet, or to control arbitration acceleration.
1. The PHY can initiate a status transfer either autonomously or in response to a register read request from the
LLC.
2. The PHY initiates a receive operation whenever a packet is received from the serial bus.
3. The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the
LLC.
4. The transmit operation is initiated when the PHY grants control of the interface to the LLC.
Table 10 and Table 11 show the encoding of the CTL0-CTL1 bus.
Table 10. CTL Encoding When PHY Has Control of the Bus
CTL0 CTL1 NAME DESCRIPTION
0 0 Idle No activity (this is the default mode)
0 1 Status Status information is being sent from the PHY to the LLC.
1 0 Receive An incoming packet is being sent from the PHY to the LLC.
1 1 Grant The LLC has been given control of the bus to send an outgoing packet.
Table 11. CTL Encoding When LLC Has Control of the Bus
CTL0 CTL1 NAME DESCRIPTION
0 0 Idle The LLC releases the bus (transmission has been completed).
The LLC is holding the bus while data is being prepared for transmission or indicating that
0 1 Hold
another packet is to be transmitted (concatenated) without arbitrating.
1 0 Transmit An outgoing packet is being sent from the LLC to the PHY.
1 1 Reserved None
LLC Service Request
To request access to the bus, to read or write a PHY register, or to send a link notification to PHY, the LLC
sends a serial bit stream on the LREQ terminal as shown in Figure 11.
Figure 11. LREQ Request Stream
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