Datasheet

TSB81BA3E

SLLS783A –MAY 2009–REVISED MAY 2010

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Therefore, in order to maintain consistent gap-count registers throughout the bus, the following rules apply to the

use of the IBR bit, RHB, and gap-count register in PHY register 1:

• Following the transmission of a PHY configuration packet, a bus reset must be initiated to verify that all nodes

have correctly updated their RHBs and gap-count register values, and to ensure that a subsequent new

connection to the bus causes the gap-count register to be set to 63 on all nodes in the bus. If this bus reset is

initiated by setting the IBR bit to 1, then the RHB and gap-count register must also be loaded with the correct

values consistent with the just-transmitted PHY configuration packet. In the TSB81BA3E, the RHB and

gap-count register have been updated to their correct values on the transmission of the PHY configuration

packet and so these values can first be read from register 1 and then rewritten.

• Other than to initiate the bus reset, which must follow the transmission of a PHY configuration packet, when

the IBR bit is set to 1 to initiate a bus reset, the gap-count register value must also be set to 63 to be

consistent with other nodes on the bus, and the RHB must be maintained with its current value.

• The PHY register 1 must not be written to except to set the IBR bit. The RHB and gap-count register must not

be written without also setting the IBR bit to 1.

• To avoid these problems, all bus resets initiated by software must be initiated by writing the ISBR bit (bit 1

PHY register 0101b). Care must be taken to not change the value of any of the other writeable bits in this

by means of the PHY configuration packet, which changes all nodes to the same gap count.

PRINCIPLES OF OPERATION (1394a-2000 INTERFACE)

The TSB81BA3E is designed to operate with an LLC such as the Texas Instruments TSB12LV21B, TSB12LV26,

TSB12LV32, TSB42AA4, or TSB12LV01B when the BMODE terminal is tied low. Details of operation for the

Texas Instruments LLC devices are found in the respective LLC data sheets. The following paragraphs describe

the operation of the PHY-LLC interface. This interface is formally defined in IEEE 1394a-2000, Section 5A.

The interface to the LLC consists of the PCLK, CTL0-CTL1, D0-D7, LREQ, LPS, and LKON/DS2 terminals on

the TSB81BA3E, as shown in Figure 10.

Figure 10. PHY-LLC Interface

The PCLK terminal provides a 49.152-MHz interface system clock. All control and data signals are synchronized

to and sampled on the rising edge of PCLK. This terminal serves the same function as the SYSCLK terminal of

1394a-2000-compliant PHY devices.

The CTL0 and CTL1 terminals form a bidirectional control bus, which controls the flow of information and data

between the TSB81BA3E and LLC.

Product Folder Link(s): TSB81BA3E