Datasheet

TSB81BA3E
www.ti.com SLLS783A –MAY 2009–REVISED MAY 2010
A variation of less than ±100 ppm from nominal for the media data rates is required by IEEE Std 1394. Adjacent
PHYs may therefore have a difference of up to 200 ppm from each other in their internal clocks, and PHYs must
be able to compensate for this difference over the maximum packet length. Larger clock variations may cause
resynchronization overflows or underflows, resulting in corrupted packet data.
For the TSB81BA3E, the PCLK output may be used to measure the frequency accuracy and stability of the
internal oscillator and PLL from which it is derived. When operating the PHY-LLC interface with a non-1394b
LLC, the frequency of the PCLK output must be within ±100 ppm of the nominal frequency of 49.152 MHz. When
operating the PHY-LLC interface with a 1394b LLC, the frequency of the PCLK output must be within ±100 ppm
of the nominal frequency of 98.304 MHz.
The following are some typical specifications for an oscillator used with the TSB81BA3E physical layer from TI to
achieve the required frequency accuracy and stability:
• RMS jitter of 5 picoseconds or better
• RMS phase noise jitter of 1 picosecond or less over the range 12 kHz to 20 MHz or better
• Frequency tolerance at 25°C: Total frequency variation for the complete circuit is ±100 ppm. A device with
±30 ppm or ±50 ppm frequency tolerance is recommended for adequate margin.
• Frequency stability (over temperature and age): A device with ±30 ppm or ±50 ppm frequency stability is
recommended for adequate margin.
NOTE
The total frequency variation must be kept below ±100 ppm from nominal with some
allowance for error introduced by board and device variations. Trade-offs between
frequency tolerance and stability may be made as long as the total frequency variation is
less than ±100 ppm. For example, the frequency tolerance of the crystal may be specified
at 50 ppm and the temperature tolerance may be specified at 30 ppm to give a total of 80
ppm possible variation due to the oscillator alone. Aging also contributes to the frequency
variation.
It is strongly recommended that part of the verification process for the design is to measure the frequency of the
PCLK output of the PHY. This should be done with a frequency counter with an accuracy of 6 digits or better.
Bus Reset
It is recommended, that when the user has a choice, the user should initiate a bus reset by writing to the
initiate-short-bus-reset (ISBR) bit (bit 1, PHY register 0101b). Care must be taken to not change the value of any
of the other writeable bits in this register when the ISBR bit is written to.
In the TSB81BA3E, the initiate-bus-reset (IBR) bit can be set to 1 to initiate a bus reset and initialization
sequence; however, it is recommended to use the ISBR bit instead. The IBR bit is located in PHY register 1
along with the root-holdoff bit (RHB) and gap-count register. As required by the 1394b Supplement, this
configuration maintains compatibility with older Texas Instruments PHY designs which were based on either the
suggested register set defined in Annex J of IEEE Std 1394-1995 or the 1394a-2000 Supplement. Therefore,
whenever the IBR bit is written, the RHB and gap-count register are also necessarily written.
It is recommended that the RHB and gap-count register only be updated by PHY configuration packets. The
TSB81BA3E is 1394a- and 1394b-compliant, and therefore, both the reception and transmission of PHY
configuration packets cause the RHB and gap-count register to be loaded, unlike older IEEE Std
1394-1995-compliant PHYs which decode only received PHY configuration packets.
The gap-count register is set to the maximum value of 63 after two consecutive bus resets without an intervening
write to the gap-count register, either by a write to PHY register 1 or by a PHY configuration packet. This
mechanism allows a PHY configuration packet to be transmitted and then a bus reset to be initiated so as to
verify that all nodes on the bus have updated their RHBs and gap-count register values, without having the
gap-count register set back to 63 by the bus reset. The subsequent connection of a new node to the bus, which
initiates a bus reset, then causes the gap-count register of each node to be set to 63. Note, however, that if a
subsequent bus reset is instead initiated by a write to register 1 to set the IBR bit, then all other nodes on the bus
have their gap-count register values set to 63, while this node's gap-count register remains set to the value just
loaded by the write to PHY register 1.
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