Datasheet

TSB81BA3E
SLLS783A –MAY 2009–REVISED MAY 2010 www.ti.com
The TSB81BA3E also functions with a LLC that is compliant with the older 1394 standards. This interface is
compatible with both the older Annex J interface specified in the IEEE Std 1394--1995 (with the exception of the
Annex J isolation interfacing method) and the PHY-LLC interface specified in 1394a--2000. When using a LLC
compliant with this interface, the BMODE input must be tied low.
Using the TSB81BA3E With a 1394-1995 or 1394a-2000 Link Layer
When the BMODE input is tied low, the TSB81BA3E implements the PHY-LLC interface specified in the
1394a-2000 Supplement. This interface is based on the interface described in informative Annex J of IEEE Std
1394-1995, which is the interface used in the oldest Texas Instruments PHY devices. The PHY-LLC interface
specified in 1394a-2000 is compatible with the older Annex J. However, the TSB81BA3E does not support the
Annex J isolation interfacing method. When implementing the 1394a-2000 interface, certain signals are not used:
• The PINT output (terminal 1) can be left open.
• The LCLK_PMC input (terminal 7) must be tied directly to ground or through a pulldown resistor of ~1 kΩ or
less, unless the PMC mode is desired (see LCLK_PMC terminal description).
All other signals are connected to their counterparts on the 1394a link-layer controller. The PCLK output
corresponds to the SCLK input signal on most LLCs.
The 1394a-2000 Supplement includes enhancements to the Annex J interface that should be comprehended
when using the TSB81BA3E with a 1394-1995 LLC device.
• A new LLC service request was added which allows the LLC to temporarily enable and disable asynchronous
arbitration accelerations. If the LLC does not implement this new service request, then the arbitration
enhancements must not be enabled (see the EAA bit in PHY register 5).
• The capability to perform multispeed concatenation (the concatenation of packets of differing speeds) was
added to improve bus efficiency (primarily during isochronous transmission). If the LLC does not support
multispeed concatenation, then multispeed concatenation must not be enabled in the PHY (see the EMC bit
in PHY register 5).
• To accommodate the higher transmission speeds expected in future revisions of the standard, 1394a-2000
extended the speed code in bus requests from 2 bits to 3 bits, increasing the length of the bus request from 7
bits to 8 bits. The new speed codes were carefully selected so that new 1394a-2000 PHY and LLC devices
would be compatible, for speeds from S100 to S400, with legacy PHY and LLC devices that use the 2-bit
speed codes. The TSB81BA3E correctly interprets both 7-bit bus requests (with 2-bit speed code) and 8-bit
bus requests (with 3-bit speed codes). Moreover, if a 7-bit bus request is immediately followed by another
request (for example, a register read or write request), then the TSB81BA3E correctly interprets both
requests. Although the TSB81BA3E correctly interprets 8-bit bus requests, a request with a speed code
exceeding S400 while in 1394a-2000 PHY-link interface mode results in the TSB81BA3E transmitting a null
packet (data prefix followed by data end, with no data in the packet).
Power-Up Reset
To ensure proper operation of the TSB81BA3E, the RESET terminal must be asserted low for a minimum of
2 ms from the time that PHY power reaches the minimum required supply voltage and the input clock to the PHY
is valid. When using a passive capacitor on the RESET terminal to generate a power-on-reset signal, the
minimum reset time is ensured if the value of the capacitor satisfies the following equation (the value must be no
smaller than approximately 0.1 mF):
C
min
= (0.0077 × T) + 0.085 + (external_oscillator_start-up_time × 0.05)
where C
min
is the minimum capacitance on the RESETz terminal in mF, T is the V
DD
ramp time, 10%−90%, in ms,
external_oscillator_start-up_time is the time from power applied to the external oscillator till the oscillator outputs
a valid clock in ms. If a fundamental mode crystal is used rather than an oscillator then the start−up time
parameter may be set to zero.
Crystal Selection
The TSB81BA3E is designed to use an external 98.304-MHz crystal oscillator connected to the XI terminal to
provide the reference clock. This clock, in turn, drives a PLL circuit that generates the various clocks required for
transmission and resynchronization of data at the S100 through S800 media data rates.
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